Patents by Inventor Wei-Chan Chang
Wei-Chan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935878Abstract: A method for manufacturing a package structure includes providing a carrier board; providing at least one die having a top surface, a bottom surface, and a side surface on the carrier board; and forming a protective layer to cover at least a portion of the side surface of the die. The die includes a substrate, a semiconductor layer, a gate structure, a source structure and a drain structure, at least one dielectric layer, and at least one pad. The semiconductor layer is disposed on the substrate. The gate structure is disposed on the semiconductor layer. The source and the drain structures are disposed on opposite sides of the gate structure. The dielectric layer covers the gate, source, and drain structures. The pad is disposed on the dielectric layer and penetrates through the dielectric layer to electrically contact with the gate, source or drain structure.Type: GrantFiled: September 10, 2021Date of Patent: March 19, 2024Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Hsiu-Mei Yu, Guang-Yuan Jiang, Cheng-Yi Hsieh, Wei-Chan Chang, Chang-Sheng Lin
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Publication number: 20230420328Abstract: A semiconductor device includes: a substrate; a seed layer disposed on the substrate; a compound semiconductor stack layer disposed on the seed layer; and a source metal layer and a drain metal layer disposed on the compound semiconductor stack layer. The semiconductor device further includes a conductive layer at least partially covering the source metal layer and the drain metal layer, and covering opposing side surfaces of the seed layer and opposing side surfaces of the compound semiconductor stack layer. The conductive layer electrically connects the seed layer and the source metal layer.Type: ApplicationFiled: June 23, 2022Publication date: December 28, 2023Applicant: Vanguard International Semiconductor CorporationInventors: Hsiu-Mei YU, Guang-Yuan JIANG, Cheng-Yi HSIEH, Wei-Chan CHANG, Chang-Sheng LIN
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Patent number: 11810804Abstract: A method of forming dice includes the following steps. First, a wafer structure is provides, which includes a substrate and a stack of semiconductor layers disposed in die regions and a scribe line region. Then, the substrate and the stack of the semiconductor layers in the scribe line region are removed to form a groove in the substrate. After the formation of the groove, the substrate is further thinned to obtain the substrate with a reduced thickness. Finally, a separation process is performed on the substrate with the reduced thickness.Type: GrantFiled: March 9, 2022Date of Patent: November 7, 2023Assignee: Vanguard International Semiconductor CorporationInventors: Hsiu-Mei Yu, Wei-Chan Chang, Chang-Sheng Lin, Chun-Yi Wu
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Publication number: 20230238308Abstract: A semiconductor structure is provided. The semiconductor structure includes a lead frame and a sub-substrate disposed on the lead frame, wherein the thickness of the sub-substrate is between 0 and 0.5 ?m. The semiconductor structure also includes an epitaxial layer disposed on the sub-substrate. The epitaxial layer includes a buffer layer, a channel layer and a barrier layer. The buffer layer is disposed between the sub-substrate and the channel layer. The channel layer is disposed between the buffer layer and the barrier layer. The semiconductor structure further includes a device layer disposed on the barrier layer and an interconnector structure electrically connected to the epitaxial layer and/or the device layer by a through hole.Type: ApplicationFiled: January 27, 2022Publication date: July 27, 2023Applicant: Vanguard International Semiconductor CorporationInventors: Hsiu-Mei YU, Guang-Yuan JIANG, Cheng-Yi HSIEH, Wei-Chan CHANG, Chang-Sheng LIN
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Publication number: 20230083337Abstract: A method for manufacturing a package structure includes providing a carrier board; providing at least one die having a top surface, a bottom surface, and a side surface on the carrier board; and forming a protective layer to cover at least a portion of the side surface of the die. The die includes a substrate, a semiconductor layer, a gate structure, a source structure and a drain structure, at least one dielectric layer, and at least one pad. The semiconductor layer is disposed on the substrate. The gate structure is disposed on the semiconductor layer. The source and the drain structures are disposed on opposite sides of the gate structure. The dielectric layer covers the gate, source, and drain structures. The pad is disposed on the dielectric layer and penetrates through the dielectric layer to electrically contact with the gate, source or drain structure.Type: ApplicationFiled: September 10, 2021Publication date: March 16, 2023Applicant: Vanguard International Semiconductor CorporationInventors: Hsiu-Mei YU, Guang-Yuan JIANG, Cheng-Yi HSIEH, Wei-Chan CHANG, Chang-Sheng LIN
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Patent number: 11588036Abstract: A chip structure includes a substrate, a bottom conductive layer, a semiconductor layer, an interlayer dielectric layer, at least one electrode, and at least one top electrode. The substrate includes in order a core layer and a composite material. The bottom conductive layer is disposed on the bottom surface of the core layer, the semiconductor layer is disposed on the substrate, and an interlayer dielectric layer is disposed on the semiconductor layer. The at least one electrode is disposed between the semiconductor layer and the interlayer dielectric layer, and the at least one top electrode is disposed on the interlayer dielectric layer and electrically coupled to the at least one electrode.Type: GrantFiled: November 11, 2020Date of Patent: February 21, 2023Assignee: Vanguard International Semiconductor CorporationInventors: Hsiu-Mei Yu, Cheng-Yi Hsieh, Wei-Chan Chang, Chang-Sheng Lin, Chun-Yi Wu
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Publication number: 20220199438Abstract: A method of forming dice includes the following steps. First, a wafer structure is provides, which includes a substrate and a stack of semiconductor layers disposed in die regions and a scribe line region. Then, the substrate and the stack of the semiconductor layers in the scribe line region are removed to form a groove in the substrate. After the formation of the groove, the substrate is further thinned to obtain the substrate with a reduced thickness. Finally, a separation process is performed on the substrate with the reduced thickness.Type: ApplicationFiled: March 9, 2022Publication date: June 23, 2022Applicant: Vanguard International Semiconductor CorporationInventors: Hsiu-Mei Yu, Wei-Chan Chang, Chang-Sheng Lin, Chun-Yi Wu
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Publication number: 20220149170Abstract: A chip structure includes a substrate, a bottom conductive layer, a semiconductor layer, an interlayer dielectric layer, at least one electrode, and at least one top electrode. The substrate includes in order a core layer and a composite material. The bottom conductive layer is disposed on the bottom surface of the core layer, the semiconductor layer is disposed on the substrate, and an interlayer dielectric layer is disposed on the semiconductor layer. The at least one electrode is disposed between the semiconductor layer and the interlayer dielectric layer, and the at least one top electrode is disposed on the interlayer dielectric layer and electrically coupled to the at least one electrode.Type: ApplicationFiled: November 11, 2020Publication date: May 12, 2022Inventors: Hsiu-Mei Yu, Cheng-Yi Hsieh, Wei-Chan Chang, Chang-Sheng Lin, Chun-Yi Wu
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Patent number: 11309201Abstract: A method of forming dice includes the following steps. First, a wafer structure is provides, which includes a substrate and a stack of semiconductor layers disposed in die regions and a scribe line region. Then, the substrate and the stack of the semiconductor layers in the scribe line region are removed to forma groove in the substrate. After the formation of the groove, the substrate is further thinned to obtain the substrate with a reduced thickness. Finally, a separation process is performed on the substrate with the reduced thickness.Type: GrantFiled: May 14, 2020Date of Patent: April 19, 2022Assignee: Vanguard International Semiconductor CorporationInventors: Hsiu-Mei Yu, Wei-Chan Chang, Chang-Sheng Lin, Chun-Yi Wu
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Publication number: 20210358786Abstract: A method of forming dice includes the following steps. First, a wafer structure is provides, which includes a substrate and a stack of semiconductor layers disposed in die regions and a scribe line region. Then, the substrate and the stack of the semiconductor layers in the scribe line region are removed to forma groove in the substrate. After the formation of the groove, the substrate is further thinned to obtain the substrate with a reduced thickness. Finally, a separation process is performed on the substrate with the reduced thickness.Type: ApplicationFiled: May 14, 2020Publication date: November 18, 2021Inventors: Hsiu-Mei Yu, Wei-Chan Chang, Chang-Sheng Lin, Chun-Yi Wu
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Publication number: 20210305143Abstract: A semiconductor structure is provided. The semiconductor structure includes a base, a seed layer, a compound semiconductor layer, a gate structure, a source structure, a drain structure, and a conductive paste. The seed layer is disposed on the base. The compound semiconductor layer is disposed on the seed layer. The gate structure is disposed on the compound semiconductor layer. The source structure and the drain structure are disposed on both sides of the gate structure. In addition, the conductive paste is disposed between the base and a lead frame, and the conductive paste extends to the side surface of the base.Type: ApplicationFiled: March 24, 2020Publication date: September 30, 2021Applicant: Vanguard International Semiconductor CorporationInventors: Chih-Yen CHEN, Hsin-Chang TSAI, Chun-Yi WU, Chia-Ching HUANG, Chih-Jen HSIAO, Wei-Chan CHANG, Francois HEBERT
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Patent number: 11133246Abstract: A semiconductor structure is provided. The semiconductor structure includes a base, a seed layer, a compound semiconductor layer, a gate structure, a source structure, a drain structure, and a conductive paste. The seed layer is disposed on the base. The compound semiconductor layer is disposed on the seed layer. The gate structure is disposed on the compound semiconductor layer. The source structure and the drain structure are disposed on both sides of the gate structure. In addition, the conductive paste is disposed between the base and a lead frame, and the conductive paste extends to the side surface of the base.Type: GrantFiled: March 24, 2020Date of Patent: September 28, 2021Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Yen Chen, Hsin-Chang Tsai, Chun-Yi Wu, Chia-Ching Huang, Chih-Jen Hsiao, Wei-Chan Chang, Francois Hebert