Patents by Inventor Wei-Chan Kung

Wei-Chan Kung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system of generating a layout including a fuse layout pattern
    Patent number: 9892221
    Abstract: A method of generating a layout usable for fabricating an integrated circuit is disclosed. The method includes generating a block layout layer usable in conjunction with a first conductive layout layer. The first conductive layout layer includes a fuse layout pattern, and the block layout layer includes a block layout pattern overlapping a portion of a fuse line portion of the fuse layout pattern. A second conductive layout layer is generated to replace the first conductive layout layer. The generating the second conductive layout layer includes performing an optical proximity correction (OPC) process on the first conductive layout layer except the portion of the fuse line portion of the fuse layout pattern corresponding to the block layout pattern.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shien-Yang Wu, Jye-Yen Cheng, Wei-Chan Kung
  • METHOD AND SYSTEM OF GENERATING LAYOUT
    Publication number: 20150067620
    Abstract: A method of generating a layout usable for fabricating an integrated circuit is disclosed. The method includes generating a block layout layer usable in conjunction with a first conductive layout layer. The first conductive layout layer includes a fuse layout pattern, and the block layout layer includes a block layout pattern overlapping a portion of a fuse line portion of the fuse layout pattern. A second conductive layout layer is generated to replace the first conductive layout layer. The generating the second conductive layout layer includes performing an optical proximity correction (OPC) process on the first conductive layout layer except the portion of the fuse line portion of the fuse layout pattern corresponding to the block layout pattern.
    Type: Application
    Filed: September 10, 2014
    Publication date: March 5, 2015
    Inventors: Shien-Yang WU, Jye-Yen CHENG, Wei-Chan KUNG
  • Electrical fuse structure and method of formation
    Patent number: 8686536
    Abstract: An embodiment is a fuse structure. In accordance with an embodiment, a fuse structure comprises an anode, a cathode, a fuse link interposed between the anode and the cathode, and cathode connectors coupled to the cathode. The cathode connectors are each equivalent to or larger than about two times a minimum feature size of a contact that couples to an active device.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shien-Yang Wu, Wei-Chan Kung
  • Electrical Fuse Structure and Method of Formation
    Publication number: 20110101493
    Abstract: An embodiment is a fuse structure. In accordance with an embodiment, a fuse structure comprises an anode, a cathode, a fuse link interposed between the anode and the cathode, and cathode connectors coupled to the cathode. The cathode connectors are each equivalent to or larger than about two times a minimum feature size of a contact that couples to an active device.
    Type: Application
    Filed: April 30, 2010
    Publication date: May 5, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shien-Yang Wu, Wei-Chan Kung
  • INTEGRATED CIRCUITS HAVING FUSES AND SYSTEMS THEREOF
    Publication number: 20100213569
    Abstract: An integrated circuit includes a fuse over a substrate. The fuse has a first end, a second end, and a central portion between the first end and the second end. A first dummy pattern is disposed adjacent to each side of the central portion of the fuse.
    Type: Application
    Filed: December 15, 2009
    Publication date: August 26, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shien-Yang WU, Jye-Yen Cheng, Wei-Chan Kung