Patents by Inventor Wei Chang
Wei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11959864Abstract: A photolithography method includes dispensing a first liquid toward a target layer through a nozzle at a first distance from the target layer; moving the nozzle such that the nozzle is at a second distance from the target layer, wherein the second distance is different from the first distance; dispensing a second liquid toward the target layer through the nozzle at the second distance from the target layer; and patterning the target layer after dispensing the first liquid and the second liquid.Type: GrantFiled: November 22, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Hung Liao, Wei Chang Cheng
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Patent number: 11961919Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.Type: GrantFiled: March 21, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Chung Chang, Hsiu-Hao Tsao, Ming-Jhe Sie, Shun-Hui Yang, Chen-Huang Huang, An Chyi Wei, Ryan Chia-Jen Chen
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Patent number: 11962328Abstract: A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.Type: GrantFiled: November 28, 2022Date of Patent: April 16, 2024Assignee: PHISON ELECTRONICS CORP.Inventors: Shih-Jia Zeng, Yi-Fang Chang, Chun-Wei Tsao, Chen-An Hsu, Wei Lin
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Patent number: 11961769Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.Type: GrantFiled: November 7, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
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Publication number: 20240117380Abstract: Provided herein are CRISPR/Cas9 complexes and method of using same.Type: ApplicationFiled: April 4, 2023Publication date: April 11, 2024Applicant: THE UAB RESEARCH FOUNDATIONInventors: Tim Townes, Lei Ding, Chia-Wei Chang
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Publication number: 20240120282Abstract: The present application discloses a semiconductor structure and methods for manufacturing semiconductor structures. The semiconductor structure includes a plurality of bottom dies and a top die stacked on the bottom dies. The bottom dies receive power supplies through tiny through silicon vias (TSVs) formed in backside substrates of the bottom dies, while the top die receives power supplies through dielectric vias (TDVs) formed in a dielectric layer that covers the bottom dies. By enabling backside power delivery to the bottom die, more space can be provided for trace routing between stacked dies. Therefore, greater computation capability can be achieved within a smaller chip area with less power loss.Type: ApplicationFiled: February 20, 2023Publication date: April 11, 2024Inventors: TZU-WEI CHIU, CHUN-WEI CHANG, SHANG-PIN CHEN, WEI-CHIH CHEN, CHE-YEN HUANG
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Publication number: 20240117054Abstract: Multi-specific binding proteins that bind NKG2D receptor, CD 16, and FLT3 are described, as well as pharmaceutical compositions and therapeutic methods useful for the treatment of autoimmune disease or cancer.Type: ApplicationFiled: October 14, 2020Publication date: April 11, 2024Inventors: Hemanta Baruah, Gregory P. Chang, Ann F. Cheung, Asya Grinberg, Zong Sean Juo, Thomas J. McQuade, Daniel Fallon, William Haney, Steven O'Neil, Ronnie Wei
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Publication number: 20240120239Abstract: A method for modulating a threshold voltage of a device. The method includes providing a fin extending from a substrate, where the fin includes a plurality of semiconductor channel layers defining a channel region for a P-type transistor. In some embodiments, the method further includes forming a first gate dielectric layer surrounding at least three sides of each of the plurality of semiconductor channel layers of the P-type transistor. Thereafter, the method further includes forming a P-type metal film surrounding the first gate dielectric layer. In an example, and after forming the P-type metal film, the method further includes annealing the semiconductor device. After the annealing, and in some embodiments, the method includes removing the P-type metal film.Type: ApplicationFiled: March 10, 2023Publication date: April 11, 2024Inventors: Cheng-Wei CHANG, Chi-Yu CHOU, Lun-Kuang TAN, Shuen-Shin LIANG
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Publication number: 20240120203Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.Type: ApplicationFiled: March 8, 2023Publication date: April 11, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Chih HSIUNG, Yun-Hua CHEN, Bing-Sian WU, Yi-Hsuan CHIU, Yu-Wei CHANG, Wen-Kuo HSIEH, Chih-Yuan TING, Huan-Just LIN
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Patent number: 11956887Abstract: A board, including a first pad area, a second pad area, a first micro heater, a second micro heater, a first heater terminal pad, a second heater terminal pad, and a third heater terminal pad, is provided. The first pad area and the second pad area respectively include at least one pad. The first micro heater and the second micro heater are respectively disposed corresponding to the first pad area and the second pad area. The first heater terminal pad and the second heater terminal pad form a loop with the first micro heater by being electrically connected to an outside, so that the first micro heater generates heat. The second heater terminal pad and the third heater terminal pad form another loop with the second micro heater by being electrically connected to the outside, so that the second micro heater generates heat. A circuit board and a fixture are also provided.Type: GrantFiled: January 27, 2022Date of Patent: April 9, 2024Assignee: Skiileux Electricity Inc.Inventors: Shang-Wei Tsai, Cheng Chieh Chang, Te Fu Chang
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Patent number: 11952540Abstract: A method and apparatus for hydrocracking mineralized refuse pyrolysis oil. The method may use the following steps: (a) crushing and pyrolyzing mineralized refuse to obtain arene and alkane precursor biomass oil; (b) hydrogenating the arene and alkane precursor biomass oil obtained in step (a), and separating the obtained hydrocrackate to obtain arene and alkane; and (c) purifying, recovering and optimizing the arene and alkane obtained in step (b), and performing deep processing to produce naphtha, jet fuel, light diesel oil, and heavy diesel oil.Type: GrantFiled: June 16, 2020Date of Patent: April 9, 2024Assignee: East China University of Science and TechnologyInventors: Yulong Chang, Hualin Wang, Xia Jiang, Jianping Li, Jingyi Zhu, Pengbo Fu, Wei Yuan
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Patent number: 11955329Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.Type: GrantFiled: April 28, 2023Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Chun-I Tsai, Ken-Yu Chang, Yi-Ying Liu
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Patent number: 11955397Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.Type: GrantFiled: November 9, 2020Date of Patent: April 9, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
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Patent number: 11953614Abstract: A method for measuring coordinate position include detecting the distance of a target relative to a portable electronic device to generate a measurement signal corresponding to the distance, sensing a relative position of the target to generate a azimuth angle corresponding to the relative position, detecting the movement of the portable electronic device to generate an inertial signal corresponding to the movement, obtaining positioning information of the portable electronic device, converting the measurement signal into distance data, converting the inertial signal into a tilt angle, calculating coordinate difference information with the tilt angle, the distance data and the azimuth angle, and calculating coordinate position of the target with the positioning information and the coordinate difference information.Type: GrantFiled: November 5, 2021Date of Patent: April 9, 2024Assignee: Getac Technology CorporationInventors: Chia-Chang Chiu, Wei-Rong Chen
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Publication number: 20240112688Abstract: The present disclosure provides an audio compression device, an audio compressing system and an audio compression method. The audio compression device comprises a first transceiver and a first processor. The first transceiver is connected to the first processor. The processor obtains an audio signal and an available bandwidth, and the processor performs an audio compression encoding on the audio signal to obtain a sample audio signal, and then compares with the audio signal and the sample audio signal to generate a residual signal, and the residual signal is transmitted according to the available bandwidth. The audio signal can be completely transmitted to an audio decompression device to reduce the distortion of the audio signal.Type: ApplicationFiled: October 4, 2022Publication date: April 4, 2024Applicant: SAVITECH CORP.Inventors: Sing-Ban Robert TIEN, Wen-Wei KANG, Wu-Lin CHANG, Chi-Feng HUANG, Lee-Chang PANG
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Publication number: 20240113154Abstract: A semiconductor device may include a compound substrate and a 3-dimensional inductor structure. The compound substrate may include a front surface and a back surface. The 3-dimensional inductor structure may include a front conductive stack, a back conductive layer, and at least one through-hole structure. At least one portion of the front conductive stack may include a first conductive layer disposed on the front surface of the compound substrate, and a second conductive layer disposed on the first conductive layer. The second conductive layer has a thickness ranging between 30 micrometers and 400 micrometers. The back conductive layer is disposed on the back surface of the compound substrate. The at least one through-hole structure penetrates through the compound substrate, and electrically connects the front conductive stack to the back conductive layer.Type: ApplicationFiled: November 20, 2022Publication date: April 4, 2024Applicant: RichWave Technology Corp.Inventors: Chia-Wei Chang, Yan-Han Huang, Chin-Chia Chang
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Publication number: 20240112360Abstract: A measurement system includes a camera and a processor. The camera is configured to capture a measurement card image of a measurement card, and the measurement card image includes a number of feature pattern images. The processor is electrically connected to the camera and configured for analyzing the feature pattern images to obtain a feature point coordinate of a feature point of each feature pattern image, and inputting the feature point coordinates into a conversion matrix to obtain a tip coordinate of a tip of the measurement card.Type: ApplicationFiled: January 18, 2023Publication date: April 4, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Wei CHANG, Shih-Fang YANG MAO, Tien-Yan MA
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Publication number: 20240109517Abstract: A wiper connection structure, comprising a connection body and an upper cover. The connection body is mounted on a wiper blade; an accommodating cavity is formed on the connection body; the accommodating cavity is opened on an upper surface and a side vertical surface of the connection body respectively to correspondingly form an upper opening and an inlet for the head of a wiper to insert into the accommodating cavity; the upper cover is hingedly connected to the upper opening, and the upper cover can sealably close and open the upper opening; in addition, at least one of the accommodating cavity and the upper cover is provided with a limiting member capable of stopping and limiting the head of the wiper, so as to ensure that the head of the wiper does not fall off from the accommodating cavity.Type: ApplicationFiled: November 8, 2021Publication date: April 4, 2024Inventor: Che-Wei CHANG
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Publication number: 20240113032Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.Type: ApplicationFiled: April 25, 2023Publication date: April 4, 2024Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
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Patent number: D1023378Type: GrantFiled: February 22, 2022Date of Patent: April 16, 2024Assignee: Acer IncorporatedInventors: Wei-Chang Chen, Jung-Wei Tsao