Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.

Abstract: Provided are probiotic compositions and methods of using such compositions for treatment of a spectrum of diseases like malnutrition. The probiotic compositions provided herein have Prevotella copri or engineered strains with genes from Prevotella copri.

Abstract: An electronic package is provided and includes at least one electronic element, at least one first conductive structure and a second conductive structure disposed on one side of a carrier structure with at least one circuit layer, and an encapsulation layer covering the electronic element, the first conductive structure and the second conductive structure, where the first conductive structure is exposed from the encapsulation layer to externally connect required elements according to functional requirements.

Abstract: A semiconductor device includes a gate structure on a semiconductor fin, a dielectric layer on the gate structure, and a gate contact extending through the dielectric layer to the gate structure. The gate contact includes a first conductive material on the gate structure, a top surface of the first conductive material extending between sidewalls of the dielectric layer, and a second conductive material on the top surface of the first conductive material.

Abstract: Some implementations described herein provide a nanostructure transistor including inner spacers between a gate structure and a source/drain region. The inner spacers, formed in cavities at end regions of sacrificial nanosheets during fabrication of the nanostructure transistor, include concave-regions that face the source/drain region. Formation techniques include forming the sacrificial nanosheets and inner spacers to include certain geometric and/or dimensional properties, such that a likelihood of defects and/or voids within the inner spacers and/or the gate structure are reduced.

Abstract: The present disclosure provides an optical element driving mechanism, which includes a first movable part, a fixed assembly, a first driving assembly and a locking assembly. The first movable part includes an optical element. The fixed assembly has a first opening, and the first movable part is movable relative to the fixed assembly. The first driving assembly is configured to drive the first movable part to move relative to the fixed assembly, so that the optical element selectively overlaps the first opening. The locking assembly is configured to fix the first movable part at a first position relative to the fixed assembly temporarily.

Abstract: A crossbow includes a string, a trigger assembly, a safety and a string-unlocking apparatus. Only one hand is required to use a cocking device to operate the string-unlocking apparatus to move the safety to an unlocking position from a locking position and to pivot the trigger assembly to a releasing position from a hooking position.

Abstract: A circuit includes a data register configured to receive and output successive data elements of a plurality of data elements responsive to a clock signal, wherein each data element of the plurality of data elements includes a total number of bits N. A signal generation portion is configured to output a first selection signal responsive to the clock signal, the first selection signal includes two alternating sequences, values of the first sequence increment from zero to N?1, and values of the second sequence decrement from N?1 to zero. A selection circuit coupled to the data register is configured to output the N bits of each data element of the plurality of data elements in a first sequential order responsive to the first sequence of the first selection signal, and in a second sequential order opposite the first sequential order responsive to the second sequence of the first selection signal.

Abstract: Embodiments relate to the field of semiconductor manufacturing technology, and more particularly, to a method for fabricating a semiconductor structure, and the semiconductor structure. The method includes: providing a substrate having a connection hole thereon, annular protrusions and annular grooves alternately arranged along a direction parallel to a center line of the connection hole being provided on a hole wall of the connection hole; filling a barrier block in each of the annular grooves; removing the annular protrusions along a direction perpendicular to the hole wall of the connection hole; removing the barrier blocks; and forming a connection layer in the connection hole. After the annular protrusions are removed, roughness of the hole wall of the connection hole is reduced, such that a conductive seed layer is prevented from being broken, thereby avoiding generation of voids in the connection layer, and improving performance of the semiconductor structure.

Abstract: An apparatus for performing a current trapper function. The apparatus includes: a short impedance structure; a first open impedance structure, the first open impedance structure being coupled between the short impedance structure and ground; and, a second open impedance structure, the second open impedance structure being coupled between the short impedance structure and ground, the short impedance structure being coupled between the first open impedance structure and the second open impedance structure. In certain embodiments, the apparatus is included within a multi radio docking station.

Abstract: The invention provides a semiconductor structure, which comprises a GaN gallium nitride (GaN) layer, an aluminum gallium nitride (AlGaN) layer on the gallium nitride layer, a polarization boost layer on and in direct contact with the aluminum gallium nitride layer, and a gate liner layer on the polarization boost layer.

Abstract: The present application discloses a semiconductor structure. The semiconductor structure a top die and a bottom die, and the maximum die size is constrained to reticle dimension. Each die includes (1) core: computation circuits, (2) phy: analog circuit connecting to memory, (3) I/O: analog circuit connecting output elements, (4) SERDES: serial high speed analog circuit, (5) intra-stack connection circuit, and (6) cache memory. This semiconductor structure can be chapleted design for high wafer yield with least tape out masks for cost saving. The intra-stack connection circuit connects the top die and the bottom die in the shortest distance (about tens of micrometers), so as to provide high signal quality and power efficiency.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.

Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.

Abstract: A system and method for image-guided microscopic illumination are provided. A processing module controls an imaging assembly such that a camera acquires an image or images of a sample in multiple fields of view, and the image or images are automatically transmitted to a processing module and processed by the first processing module automatically in real-time based on a predefined criterion so as to determine coordinate information of an interested region in each field of view. The processing module also controls an illuminating assembly to illuminate the interested region of the sample according to the received coordinate information regarding to the interested region, with the illumination patterns changing among the fields of view.

Abstract: A memory device includes a first bit cell, a second bit cell, a first word line and a second word line. A first boundary of the second bit cell is adjacent with a first boundary of the first bit cell. The first word line is coupled to the first bit cell. The second word line is coupled to the second bit cell. A first segment of the first word line is overlapped with the first boundary of the second bit cell in a plan view, and a first segment of the second word line is overlapped with a second boundary of the second bit cell in the plan view.

Abstract: A method includes: receiving a layout of an integrated circuit; identifying, based on the layout, at least a first net and at least a second net, wherein the first net extends through the integrated circuit along a vertical direction, and the second net terminates at a middle portion of the integrated circuit along the vertical direction; dividing the integrated circuit into a plurality of grid units, wherein he first net is constituted by a first subset of the plurality of grid units, and the second net is constituted by a second subset of the plurality of grid units; estimating a first thermal conductivity of each of the first subsets of grid units; estimating a second thermal conductivity of each of the second subsets of grid units; and estimating an equivalent thermal conductivity of the integrated circuit based on combining the first thermal conductivity and the second thermal conductivity.

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a cap layer on sidewalls of the first MTJ and the second MTJ, a dielectric layer around and directly contacting the cap layer, a first metal interconnection on the first MTJ, the second MTJ, and the dielectric layer, and an inter-metal dielectric (IMD) layer around the dielectric layer and the first metal interconnection.