Abstract: A resistor between dummy flash structures includes a substrate. The substrate includes a resistor region and a flash region. A first dummy memory gate structure and a second dummy memory gate structure are disposed within the resistor region of the substrate. A polysilicon resistor is disposed between the first dummy memory gate structure and the second dummy memory gate structure. The polysilicon resistor contacts the first dummy memory gate structure and the second dummy memory gate structure.

Abstract: The present disclosure provides inhibited starches, methods of making inhibited starches, and emulsions and foams including them, and food and beverage products including them.

Abstract: A semiconductor device includes a substrate having a flash memory region and a logic device region, a logic transistor disposed in the logic device region, and a flash memory transistor disposed in the flash memory region. The flash memory transistor includes a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.

Abstract: The present disclosure relates to inhibited waxy starches and methods for using them. One aspect of the disclosure is an inhibited waxy starch based on maize, wheat, or tapioca having an amylopectin content in the range of 90-100%; and a sedimentation volume in the range of 10-50 mL/g; in which the amylopectin fraction of the inhibited waxy starch based on maize, wheat, or tapioca has no more than 48.5% medium-length branches having a chain length from 13-24 (measured by a valley-to-valley method as described herein), and the starch is not pregelatinized. Methods of using the starch materials in food products are also described.

Abstract: The present disclosure relates to inhibited porous granular starches having desirably high porosity. One aspect thereof is a method for making an inhibited porous granular starch product, that includes hydrolyzing a granular starch feed to a degree of hydrolysis of 20-75% using one or more enzymes including one or more of a glucoamylase and an alpha-amylase; wherein the inhibited porous granular starch product has a porosity of 10%˜50% as measured by change in water uptake as compared to the granular starch feed and a sedimentation volume in the range of 20 mL/g to SO mL/g. Another aspect of the disclosure is inhibited porous granular starch product having a water uptake of at least 1.0 g water/g starch and a sedimentation volume in the range of 20-80 mL/g. inhibited porous granular starches can be advantaged over conventional starches in that they can have increased viscosity at lower mass loadings.

Abstract: A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.

Abstract: The present disclosure relates to inhibited waxy starches and methods for using them. One aspect of the disclosure is an inhibited waxy starch based on maize, wheat, or tapioca having an amylopectin content in the range of 90-100%; and a sedimentation volume in the range of 10-50 mL/g; in which the amylopectin fraction of the inhibited waxy starch based on maize, wheat, or tapioca has no more than 48.5% medium-length branches having a chain length from 13-24 (measured by a valley-to-valley method as described herein), and the starch is not pregelatinized. Methods of using the starch materials in food products are also described.

Abstract: The present disclosure relates to inhibited waxy starches and methods for using them. One aspect of the disclosure is an inhibited waxy starch based on maize, wheat, or tapioca having an amylopectin content in the range of 90-100%; and a sedimentation volume in the range of 10-50 mL/g; in which the amylopectin fraction of the inhibited waxy starch based on maize, wheat, or tapioca has no more than 48.5% medium-length branches having a chain length from 13-24 (measured by a valley-to-valley method as described herein), and the starch is not pregelatinized. Methods of using the starch materials in food products are also described.

Abstract: A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.

Abstract: A method of integrating memory and metal-oxide-semiconductor (MOS) processes is provided, including steps of forming an oxide layer and a nitride layer on a substrate, forming a field oxide in a first area by an oxidation process with the nitride layer as a mask, wherein the oxidation process simultaneously forms a top oxide layer on the nitride layer, removing the top oxide layer, the nitride layer and the oxide layer in the first area, forming a polysilicon layer on the substrate, and patterning the polysilicon layer into MOS units in the first area and memory units in a second area.

Abstract: The present disclosure relates to low-color waxy tapioca starches and methods for making and using them. A method for preventing color formation in a waxy tapioca starch, the method comprising providing a waxy tapioca starch, and contacting the waxy tapioca starch with an aqueous decolorizing liquid, the aqueous decolorizing liquid being selected from the group consisting of an aqueous alkaline liquid, and an aqueous surfactant liquid; and substantially removing the aqueous decolorizing liquid from the waxy tapioca starch.

Abstract: The present disclosure relates to inhibited waxy starches and methods for using them. One aspect of the disclosure is an inhibited waxy starch based on maize, wheat, or tapioca having an amylopectin content in the range of 90-100%; and a sedimentation volume in the range of 10-50 mL/g; in which the amylopectin fraction of the inhibited waxy starch based on maize, wheat, or tapioca has no more than 48.5% medium-length branches having a chain length from 13-24 (measured by a valley-to-valley method as described herein), and the starch is not pregelatinized. Methods of using the starch materials in food products are also described.

Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.

Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device formed from the manufacturing method includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge.

Abstract: A flash memory includes a substrate, a memory gate on the substrate, a charge-storage layer between the memory gate and the substrate, a select gate adjacent to the memory gate, a select gate dielectric layer between the select gate and the substrate, a first oxide-nitride spacer between the memory gate and the select gate, and a second oxide-nitride spacer. The select gate includes an upper portion and a lower portion. The second oxide-nitride spacer is disposed between the first oxide-nitride spacer and the upper portion of the select gate.

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device formed from the manufacturing method includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge.

Abstract: A semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge. Additionally, a method of manufacturing the semiconductor memory device is also provided.

Abstract: A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.

Abstract: A flash cell forming process includes the following steps. A first gate is formed on a substrate. A first spacer is formed at a side of the first gate, where the first spacer includes a bottom part and a top part. The bottom part is removed, thereby an undercut being formed. A first selective gate is formed beside the first spacer and fills into the undercut. The present invention also provides a flash cell formed by said flash cell forming process. The flash cell includes a first gate, a first spacer and a first selective gate. The first gate is disposed on a substrate. The first spacer is disposed at a side of the first gate, where the first spacer has an undercut at a bottom part, and therefore exposes the substrate. The first selective gate is disposed beside the first spacer and extends into the undercut.