Patents by Inventor Weichang Liu
Weichang Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11896038Abstract: The present disclosure relates to inhibited waxy starches and methods for using them. One aspect of the disclosure is an inhibited waxy starch based on maize, wheat, or tapioca having an amylopectin content in the range of 90-100%; and a sedimentation volume in the range of 10-50 mL/g; in which the amylopectin fraction of the inhibited waxy starch based on maize, wheat, or tapioca has no more than 48.5% medium-length branches having a chain length from 13-24 (measured by a valley-to-valley method as described herein), and the starch is not pregelatinized. Methods of using the starch materials in food products are also described.Type: GrantFiled: September 1, 2021Date of Patent: February 13, 2024Assignee: Tate & Lyle Solutions USA LLCInventors: Judith K. Whaley, Weichang Liu, Yuqing Zhou, Xian Chen, Leslie George Howarth, Mark Beltz
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Publication number: 20240002548Abstract: The present disclosure relates to inhibited porous granular starches having desirably high porosity. One aspect thereof is a method for making an inhibited porous granular starch product, that includes hydrolyzing a granular starch feed to a degree of hydrolysis of 20-75% using one or more enzymes including one or more of a glucoamylase and an alpha-amylase; wherein the inhibited porous granular starch product has a porosity of 10%˜50% as measured by change in water uptake as compared to the granular starch feed and a sedimentation volume in the range of 20 mL/g to SO mL/g. Another aspect of the disclosure is inhibited porous granular starch product having a water uptake of at least 1.0 g water/g starch and a sedimentation volume in the range of 20-80 mL/g. inhibited porous granular starches can be advantaged over conventional starches in that they can have increased viscosity at lower mass loadings.Type: ApplicationFiled: March 24, 2021Publication date: January 4, 2024Inventors: Zheng You, Weichang Liu, Saravanan Suppiah Singaram, Jarred Lawson
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Patent number: 11444095Abstract: A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.Type: GrantFiled: April 13, 2021Date of Patent: September 13, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wang Xiang, Chia-Ching Hsu, Shen-De Wang, Weichang Liu
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Publication number: 20210392930Abstract: The present disclosure relates to inhibited waxy starches and methods for using them. One aspect of the disclosure is an inhibited waxy starch based on maize, wheat, or tapioca having an amylopectin content in the range of 90-100%; and a sedimentation volume in the range of 10-50 mL/g; in which the amylopectin fraction of the inhibited waxy starch based on maize, wheat, or tapioca has no more than 48.5% medium-length branches having a chain length from 13-24 (measured by a valley-to-valley method as described herein), and the starch is not pregelatinized. Methods of using the starch materials in food products are also described.Type: ApplicationFiled: September 1, 2021Publication date: December 23, 2021Inventors: Judith K. Whaley, Weichang Liu, Yuqing Zhou, Xian Chen, Leslie George Howarth, Mark Beltz
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Patent number: 11129402Abstract: The present disclosure relates to inhibited waxy starches and methods for using them. One aspect of the disclosure is an inhibited waxy starch based on maize, wheat, or tapioca having an amylopectin content in the range of 90-100%; and a sedimentation volume in the range of 10-50 mL/g; in which the amylopectin fraction of the inhibited waxy starch based on maize, wheat, or tapioca has no more than 48.5% medium-length branches having a chain length from 13-24 (measured by a valley-to-valley method as described herein), and the starch is not pregelatinized. Methods of using the starch materials in food products are also described.Type: GrantFiled: December 15, 2017Date of Patent: September 28, 2021Assignee: Tate & Lyle Ingredients Americas LLCInventors: Judith K. Whaley, Weichang Liu, Yuqing Zhou, Xian Chen, Leslie George Howarth, Mark Beltz
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Publication number: 20210233924Abstract: A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.Type: ApplicationFiled: April 13, 2021Publication date: July 29, 2021Inventors: Wang Xiang, Chia-Ching Hsu, Shen-De Wang, Weichang Liu
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Patent number: 11011535Abstract: A method of integrating memory and metal-oxide-semiconductor (MOS) processes is provided, including steps of forming an oxide layer and a nitride layer on a substrate, forming a field oxide in a first area by an oxidation process with the nitride layer as a mask, wherein the oxidation process simultaneously forms a top oxide layer on the nitride layer, removing the top oxide layer, the nitride layer and the oxide layer in the first area, forming a polysilicon layer on the substrate, and patterning the polysilicon layer into MOS units in the first area and memory units in a second area.Type: GrantFiled: December 22, 2019Date of Patent: May 18, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wang Xiang, Chia-Ching Hsu, Shen-De Wang, Weichang Liu
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Publication number: 20200385493Abstract: The present disclosure relates to low-color waxy tapioca starches and methods for making and using them. A method for preventing color formation in a waxy tapioca starch, the method comprising providing a waxy tapioca starch, and contacting the waxy tapioca starch with an aqueous decolorizing liquid, the aqueous decolorizing liquid being selected from the group consisting of an aqueous alkaline liquid, and an aqueous surfactant liquid; and substantially removing the aqueous decolorizing liquid from the waxy tapioca starch.Type: ApplicationFiled: December 20, 2018Publication date: December 10, 2020Inventors: Weichang Liu, Zheng You, Penelope A. Patton, Michael A. Cobby, Tim Windebank, Serge Lochtman, Mariana Perez Herrera, James Smoot
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Publication number: 20190380370Abstract: The present disclosure relates to inhibited waxy starches and methods for using them. One aspect of the disclosure is an inhibited waxy starch based on maize, wheat, or tapioca having an amylopectin content in the range of 90-100%; and a sedimentation volume in the range of 10-50 mL/g; in which the amylopectin fraction of the inhibited waxy starch based on maize, wheat, or tapioca has no more than 48.5% medium-length branches having a chain length from 13-24 (measured by a valley-to-valley method as described herein), and the starch is not pregelatinized. Methods of using the starch materials in food products are also described.Type: ApplicationFiled: December 15, 2017Publication date: December 19, 2019Inventors: Judith K. Whaley, Weichang Liu, Yuqing Zhou, Xian Chen, Leslie George Howarth, Mark Beltz
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Patent number: 10332884Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.Type: GrantFiled: November 2, 2017Date of Patent: June 25, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Liang Yi, Che-Jung Hsu, Yu-Cheng Tung, Jianjun Yang, Yuan-Hsiang Chang, Chih-Chien Chang, Weichang Liu, Shen-De Wang, Kok Wun Tan
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Publication number: 20190131302Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.Type: ApplicationFiled: November 2, 2017Publication date: May 2, 2019Inventors: Liang Yi, Che-Jung Hsu, Yu-Cheng Tung, JIANJUN YANG, Yuan-Hsiang Chang, Chih-Chien Chang, WEICHANG LIU, Shen-De Wang, KOK WUN TAN
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Patent number: 10121869Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device formed from the manufacturing method includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge.Type: GrantFiled: December 5, 2017Date of Patent: November 6, 2018Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Weichang Liu, Zhen Chen, Shen-De Wang, Wang Xiang, Wei Ta
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Patent number: 9978758Abstract: A flash memory includes a substrate, a memory gate on the substrate, a charge-storage layer between the memory gate and the substrate, a select gate adjacent to the memory gate, a select gate dielectric layer between the select gate and the substrate, a first oxide-nitride spacer between the memory gate and the select gate, and a second oxide-nitride spacer. The select gate includes an upper portion and a lower portion. The second oxide-nitride spacer is disposed between the first oxide-nitride spacer and the upper portion of the select gate.Type: GrantFiled: June 2, 2017Date of Patent: May 22, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Weichang Liu, Zhen Chen, Shen-De Wang, Wang Xiang, Wei Ta, Chuan Sun
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Publication number: 20180108744Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device formed from the manufacturing method includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge.Type: ApplicationFiled: December 5, 2017Publication date: April 19, 2018Inventors: WEICHANG LIU, ZHEN CHEN, SHEN-DE WANG, WANG XIANG, WEI TA
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Patent number: 9865693Abstract: A semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge. Additionally, a method of manufacturing the semiconductor memory device is also provided.Type: GrantFiled: August 4, 2016Date of Patent: January 9, 2018Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Weichang Liu, Zhen Chen, Shen-De Wang, Wang Xiang, Wei Ta
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Patent number: 9660106Abstract: A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.Type: GrantFiled: August 18, 2014Date of Patent: May 23, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Weichang Liu, Zhen Chen, Shen-De Wang, Wei Ta, Yi-Shan Chiu, Yuan-Hsiang Chang
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Patent number: 9455322Abstract: A flash cell forming process includes the following steps. A first gate is formed on a substrate. A first spacer is formed at a side of the first gate, where the first spacer includes a bottom part and a top part. The bottom part is removed, thereby an undercut being formed. A first selective gate is formed beside the first spacer and fills into the undercut. The present invention also provides a flash cell formed by said flash cell forming process. The flash cell includes a first gate, a first spacer and a first selective gate. The first gate is disposed on a substrate. The first spacer is disposed at a side of the first gate, where the first spacer has an undercut at a bottom part, and therefore exposes the substrate. The first selective gate is disposed beside the first spacer and extends into the undercut.Type: GrantFiled: September 22, 2015Date of Patent: September 27, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Shan Chiu, Shen-De Wang, Weichang Liu, Wei Ta, Zhen Chen, Wang Xiang
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Publication number: 20160172200Abstract: A method for fabricating non-volatile memory device is disclosed. The method includes the steps of: providing a substrate having a stack structure thereon; performing a first oxidation process to form a first oxide layer on the substrate and the stack structure; etching the first oxide layer for forming a first spacer adjacent to the stack structure; performing a second oxidation process to form a second oxide layer on the substrate; forming a dielectric layer on the first spacer and the second oxide layer; and etching the dielectric layer for forming a second spacer.Type: ApplicationFiled: December 15, 2014Publication date: June 16, 2016Inventors: WEICHANG LIU, ZHEN CHEN, Shen-De Wang, Wei Ta, Yi-Shan Chiu, Yuan-Hsiang Chang, Chih-Chien Chang
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Patent number: 9324724Abstract: The present invention provides a method of fabricating a memory structure, especially forming an oxide on top of a spacer to prevent the spacer from being over-etched, the method comprising the steps of: providing a semiconductor substrate; forming a charge trapping layer, a first conducting layer and a capping layer as a gate stack on the substrate; forming a first gate structure by patterning; a plurality of spacers are patterned and disposed adjacent to the sidewall of said gate stack; depositing a second conducting layer on the substrate to cover the first gate structure and the spacer; selectively etching the second conducting layer to expose the top of the spacer; performing an oxidation process to form an oxide on top of the spacer.Type: GrantFiled: September 21, 2015Date of Patent: April 26, 2016Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Weichang Liu, Zhen Chen, Shen-De Wang, Wei Ta, Wang Xiang, Yi-Shan Chiu
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Publication number: 20160049525Abstract: A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.Type: ApplicationFiled: August 18, 2014Publication date: February 18, 2016Inventors: Weichang Liu, Zhen Chen, Shen-De Wang, Wei Ta, Yi-Shan Chiu, Yuan-Hsiang Chang