Abstract: A substrate structure having a solder mask and a process for making the same, including (a) providing a substrate having a top surface, the top surface having a die pad and a plurality of solder pads; (b) forming a first solder mask on the top surface, the first solder mask having a plurality of openings, each opening corresponding to each solder pad so as to expose at least part of the solder pad; and (c) forming a second solder mask on the first solder mask. The substrate structure can be used for packaging a thicker die so as to prevent the die crack and the overflow of molding compound will be avoided.

Abstract: A system-in-package structure includes a carrier substrate having a molding area and a periphery area, at least a chip disposed in the molding area, an encapsulation covering the chip and the molding area, a plurality of solder pads disposed in the periphery area, and a solder mask disposed in the periphery area and partially exposing the surface of the solder pads. The solder mask includes at least a void therein.

Abstract: The present invention relates to a substrate structure having a solder mask and a process for making the same. The process comprises: (a) providing a substrate having a top surface, the top surface having a die pad and a plurality of solder pads; (b) forming a first solder mask on the top surface, the first solder mask having a plurality of openings, each opening corresponding to each solder pad so as to expose at least part of the solder pad; and (c) forming a second solder mask on the first solder mask. Whereby, the substrate structure of the invention can be used for packaging a thicker die so as to prevent the die crack and the overflow of molding compound will be avoided.

Abstract: A system-in-package structure includes a carrier substrate having a molding area and a periphery area, at least a chip disposed in the molding area, an encapsulation covering the chip and the molding area, a plurality of solder pads disposed in the periphery area, and a solder mask disposed in the periphery area and partially exposing the surface of the solder pads. The solder mask includes at least a void therein.

Abstract: The present invention relates to a die package and method for making the same. The method of the invention comprises the steps of: (a) providing a plate, having a first surface and a second surface; (b) forming a plurality of first dice on the plate, the first dice having a first surface and a second surface; (c) forming a plurality of bumps on the first surface of the first dice; and (d) cutting the plate to form a plurality of die modules, each module comprising a plate unit, a first die and a plurality of bumps, the first die disposed on a first surface of the plate unit, whereby the bumps could be easily mounted on the single die.

Abstract: A method for balancing molding flow during the assembly of semiconductor packages with defective carrying units includes providing a chip carrier, which includes a number of good carrying units and at least a defective carrying unit. Then, a number of chips are attached to the good carrying units of the chip carrier, and a chip-imitative glue is formed on the defective carrying unit of the chip carrier. Next, a molding compound is formed on the chip carrier via molding to seal the chips and the chip-imitative glue, thereby improving the balance of molding flow.

Abstract: A substrate is provided for carrying at least a semiconductor device. The substrate mainly includes a carrier body, a plurality of contact pads, a solder mask and a plurality of dams of a mesh. The contact pads are disposed on a surface of the carrier body and each has a bonding surface exposed out of the solder mask for connecting with the external terminals of the semiconductor device. The dams are disposed above the surface of the carrier body. The dams protrude from and located between the bonding surfaces of the contact pads to prevent solder paste, flux or the external terminals of the semiconductor device from bridging.

Abstract: The present invention relates to a method for stacking BGA packages. At first, a first BGA package is provided. The first BGA package includes a first substrate, at least one first chip and a plurality of first connecting balls. The first substrate has a first upper surface and a first bottom surface. The first chip is disposed on the first upper surface. The first connecting balls are disposed on a plurality of first connecting pads of the first upper surface. Then, a second BGA package is provided. The second BGA package includes a second substrate, at least one second chip and a plurality of second connecting balls. The second substrate has a second upper surface and a second bottom surface. The second connecting balls are disposed on a plurality of second connecting pads of the second bottom surface. The second BGA package is stacked on the first BGA package for the second connecting balls to contact the corresponding first connecting balls.

Abstract: A method for balancing molding flow during the assembly of semiconductor packages with defective carrying units includes providing a chip carrier, which includes a number of good carrying units and at least a defective carrying unit. Then, a number of chips are attached to the good carrying units of the chip carrier, and a chip-imitative glue is formed on the defective carrying unit of the chip carrier. Next, a molding compound is formed on the chip carrier via molding to seal the chips and the chip-imitative glue, thereby improving the balance of molding flow.

Abstract: A process for fabricating a multi-chip package module is disclosed. A substrate, at least a first chip and at least a second chip are provided. The backside of the first chip is attached to a die pad on a substrate. A wire-bonding operation is carried out to electrically connect the first chip and the substrate through conductive wires. A plurality of bumps is bonded to the second chip so that one end of each bump is bonded to a contact on the second chip. Thereafter, the other end of each bump is bonded to a contact on the substrate so that the second chip and the substrate are physically and electrically connected together. Finally, an encapsulation process is performed to form a packaging material enclosing the first chip, the second chip, the conductive wires, the bumps and the substrate.

Abstract: A substrate is provided for carrying at least a semiconductor device. The substrate mainly includes a carrier body, a plurality of contact pads, a solder mask and a plurality of dams of a mesh. The contact pads are disposed on a surface of the carrier body and each has a bonding surface exposed out of the solder mask for connecting with the external terminals of the semiconductor device. The dams are disposed above the surface of the carrier body. The dams protrude from and located between the bonding surfaces of the contact pads to prevent solder paste, flux or the external terminals of the semiconductor device from bridging.

Abstract: A flip chip package mainly comprises a chip, a leadless lead frame. The leadless lead frame has a die paddle and a plurality of leads. The active surface of the chip has a plurality of bonding pads formed thereon. Besides, a plurality of bumps formed on the bonding pads are electrically connected to the chip, the leads and the die paddle. Therein, the die paddle electrically connected to the chip via the bumps not only prevents the chip from being dislocated but also provides another grounding and heat transmission paths to enhance the electrical, thermal and mechanical performance of the flip chip package. Similarly, the bumps formed on the bonding pads of the chip are electrically connected to the leads so as to fix the chip to the lead frame more securely.

Abstract: A process for fabricating a multi-chip package module is disclosed. A substrate, at least a first chip and at least a second chip are provided. The backside of the first chip is attached to a die pad on a substrate. A wire-bonding operation is carried out to electrically connect the first chip and the substrate through conductive wires. A plurality of bumps is bonded to the second chip so that one end of each bump is bonded to a contact on the second chip. Thereafter, the other end of each bump is bonded to a contact on the substrate so that the second chip and the substrate are physically and electrically connected together. Finally, an encapsulation process is performed to form a packaging material enclosing the first chip, the second chip, the conductive wires, the bumps and the substrate.

Abstract: A flip chip package mainly comprises a chip, a leadless lead frame. The leadless lead frame has a die paddle and a plurality of leads. The active surface of the chip has a plurality of bonding pads formed thereon. Besides, a plurality of bumps formed on the bonding pads are electrically connected to the chip, the leads and the die paddle. Therein, the die paddle electrically connected to the chip via the bumps not only prevents the chip from being dislocated but also provides another grounding and heat transmission paths to enhance the electrical, thermal and mechanical performance of the flip chip package. Similarly, the bumps formed on the bonding pads of the chip are electrically connected to the leads so as to fix the chip to the lead frame more securely.

Abstract: A system in package structure includes a first substrate, a first chip, a first heat-dissipating component, a second substrate, and a second chip. In this case, the first chip is formed on and electrically connected to the first substrate, and the first heat-dissipating component having a heat-conducting portion is formed above the first chip. The second chip is formed on and electrically connected to the second substrate. The second substrate is set above the first heat-dissipating component and electrically connected to the first substrate.