Patents by Inventor Wei-Che Huang

Wei-Che Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973054
    Abstract: A method for transferring an electronic device includes steps as follows. A flexible carrier is provided and has a surface with a plurality of electronic devices disposed thereon. A target substrate is provided corresponding to the surface of the flexible carrier. A pin is provided, and a pin end thereof presses on another surface of the flexible carrier without the electronic devices disposed thereon, so that the flexible carrier is deformed, causing at least one of the electronic devices to move toward the target substrate and to be in contact with the target substrate. A beam is provided to transmit at least a portion of the pin and emitted from the pin end to melt a solder. The electronic device is fixed on the target substrate by soldering. The pin is moved to restore the flexible carrier to its original shape, allowing the electronic device fixed by soldering to separate from the carrier.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: April 30, 2024
    Assignee: Stroke Precision Advanced Engineering Co., Ltd.
    Inventors: Yu-Min Huang, Sheng Che Huang, Chingju Lin, Wei-Hao Wang
  • Publication number: 20230307316
    Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface. A semiconductor device is mounted on the top surface of the substrate. The semiconductor device has an active front surface directly facing the substrate, and an opposite rear surface. A vapor chamber lid is in thermal contact with the rear surface of the semiconductor device. The vapor chamber lid includes an internal vacuum-sealed cavity that stores a working fluid, and wick structures for recirculating the working fluid within the internal vacuum-sealed cavity.
    Type: Application
    Filed: March 1, 2023
    Publication date: September 28, 2023
    Applicant: MEDIATEK INC.
    Inventors: Chin-Lai Chen, Wei-Che Huang, Wen-Sung Hsu, Chun-Yin Lin, Li-Song Lin, Tai-Yu Chen
  • Patent number: 11728292
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces close to the first surface of the first RDL structure. An antenna pattern is disposed close to the second surface of the first RDL structure. A first semiconductor die is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: August 15, 2023
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu, Wei-Che Huang, Che-Ya Chou
  • Publication number: 20220406921
    Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.
    Type: Application
    Filed: August 22, 2022
    Publication date: December 22, 2022
    Inventors: Cheng-Tien WAN, Yao-Tsung HUANG, Yun-San HUANG, Ming-Cheng LEE, Wei-Che HUANG
  • Patent number: 11450756
    Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: September 20, 2022
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Tien Wan, Yao-Tsung Huang, Yun-San Huang, Ming-Cheng Lee, Wei-Che Huang
  • Patent number: 11348900
    Abstract: A package structure comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die, provided on a second surface of the substrate; a connecting layer, provided on the first die; a second die, provided on the connecting layer, wherein the connecting layer comprises at least one bump for connecting the first die; and at least one bonding wire. The connecting layer has a first touch side and a second touch side, the first touch side contacts a first surface of the first die and the second touch side contacts a second surface of the second die, an area of the first touch side is smaller than which for the first surface of the first die, and a size of the first die equals to which of the second die.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: May 31, 2022
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Yu-Hua Huang, Wei-Che Huang, Ming-Tzong Yang
  • Publication number: 20200388700
    Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.
    Type: Application
    Filed: August 25, 2020
    Publication date: December 10, 2020
    Inventors: Cheng-Tien WAN, Yao-Tsung HUANG, Yun-San HUANG, Ming-Cheng LEE, Wei-Che HUANG
  • Patent number: 10790380
    Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: September 29, 2020
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Tien Wan, Yao-Tsung Huang, Yun-San Huang, Ming-Cheng Lee, Wei-Che Huang
  • Publication number: 20200303352
    Abstract: A package structure comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die, provided on a second surface of the substrate; a connecting layer, provided on the first die; a second die, provided on the connecting layer, wherein the connecting layer comprises at least one bump for connecting the first die; and at least one bonding wire. The connecting layer has a first touch side and a second touch side, the first touch side contacts a first surface of the first die and the second touch side contacts a second surface of the second die, an area of the first touch side is smaller than which for the first surface of the first die, and a size of the first die equals to which of the second die.
    Type: Application
    Filed: June 11, 2020
    Publication date: September 24, 2020
    Applicant: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Yu-Hua Huang, Wei-Che Huang, Ming-Tzong Yang
  • Patent number: 10727202
    Abstract: A package structure comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die, provided on a second surface of the substrate; a connecting layer, provided on the first die; a second die, provided on the connecting layer, wherein the connecting layer comprises at least one bump for connecting the first die; and at least one bonding wire. The connecting layer has a first touch side and a second touch side, the first touch side contacts a first surface of the first die and the second touch side contacts a second surface of the second die, an area of the first touch side is smaller than which for the first surface of the first die, and a size of the first die equals to which of the second die.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: July 28, 2020
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Yu-Hua Huang, Wei-Che Huang, Ming-Tzong Yang
  • Patent number: 10692789
    Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: June 23, 2020
    Assignee: MediaTek Inc.
    Inventors: Nai-Wei Liu, Tzu-Hung Lin, I-Hsuan Peng, Ching-Wen Hsiao, Wei-Che Huang
  • Publication number: 20200168572
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces close to the first surface of the first RDL structure. An antenna pattern is disposed close to the second surface of the first RDL structure. A first semiconductor die is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.
    Type: Application
    Filed: January 31, 2020
    Publication date: May 28, 2020
    Applicant: MediaTek Inc.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu, Wei-Che Huang, Che-Ya Chou
  • Patent number: 10483211
    Abstract: A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die is disposed on and electrically coupled to the first surface of the first RDL structure. A first molding compound is disposed on the first surface of the first RDL structure and surrounds the first semiconductor die. A plurality of solder balls or conductive pillar structures is disposed in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure. A method for forming the semiconductor package is also provided.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: November 19, 2019
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Ching-Wen Hsiao, Nai-Wei Liu, Wei-Che Huang
  • Patent number: 10468341
    Abstract: A semiconductor package assembly includes a redistribution layer (RDL) structure, which RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace, and the RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The RDL structure includes a first region for a semiconductor die to be disposed thereon and a second region surrounding the first region, and the extended wing portion of the RDL contact pad is offset from a center of the first region.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: November 5, 2019
    Assignee: MEDIATEK INC.
    Inventors: Nai-Wei Liu, Tzu-Hung Lin, I-Hsuan Peng, Che-Hung Kuo, Che-Ya Chou, Wei-Che Huang
  • Publication number: 20190252351
    Abstract: A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die and a first molding compound that surrounds the first semiconductor die are disposed on the first surface of the first RDL structure. An IMD structure having a conductive layer with an antenna pattern or a conductive shielding layer is disposed on the first molding compound and the first semiconductor die.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 15, 2019
    Applicant: MediaTek Inc.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu, Ching-Wen Hsiao, Wei-Che Huang
  • Patent number: 10332830
    Abstract: A semiconductor package assembly having a first semiconductor package, with a first redistribution layer (RDL) structure, a first semiconductor die having through silicon via (TSV) interconnects formed passing therethrough coupled to the first RDL structure, and a second semiconductor package stacked on the first semiconductor package with a second redistribution layer (RDL) structure. The assembly further includes a second semiconductor die without through silicon via (TSV) interconnects formed passing therethrough, coupled to the second RDL structure, and a third semiconductor package stacked on the second semiconductor package, having a third redistribution layer (RDL) structure, a third semiconductor die without through silicon via (TSV) interconnects formed passing therethrough coupled to the third RDL structure.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: June 25, 2019
    Assignee: MEDIATEK INC.
    Inventors: Ming-Tzong Yang, Wei-Che Huang, Tzu-Hung Lin
  • Publication number: 20190131233
    Abstract: A semiconductor package assembly includes a redistribution layer (RDL) structure, which RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace, and the RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The RDL structure includes a first region for a semiconductor die to be disposed thereon and a second region surrounding the first region, and the extended wing portion of the RDL contact pad is offset from a center of the first region.
    Type: Application
    Filed: December 26, 2018
    Publication date: May 2, 2019
    Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Che-Hung KUO, Che-Ya CHOU, Wei-Che HUANG
  • Publication number: 20190123176
    Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.
    Type: Application
    Filed: September 5, 2018
    Publication date: April 25, 2019
    Inventors: Cheng-Tien WAN, Yao-Tsung HUANG, Yun-San HUANG, Ming-Cheng LEE, Wei-Che HUANG
  • Patent number: 10217723
    Abstract: A semiconductor chip package includes a first die and a second die. The first die and second die are coplanar and disposed in proximity to each other in a side-by-side fashion. A non-straight line shaped interface gap is disposed between the first die and second die. A molding compound surrounds the first die and second die. A redistribution layer (RDL) structure is disposed on the first die, the second die and on the molding compound. The first semiconductor die is electrically connected to the second semiconductor die through the RDL structure.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: February 26, 2019
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu, Wei-Che Huang
  • Patent number: 10199318
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure. The RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace. The RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The extended wing portion overlaps at least one-half of a boundary of the symmetrical portion when observed from a plan view.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: February 5, 2019
    Assignee: MEDIATEK INC.
    Inventors: Nai-Wei Liu, Tzu-Hung Lin, I-Hsuan Peng, Che-Hung Kuo, Che-Ya Chou, Wei-Che Huang