Patents by Inventor Wei-Chen Chien

Wei-Chen Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10366200
    Abstract: A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes generating a first layout of the integrated circuit based on design criteria, generating a standard cell layout of the integrated circuit, generating a via color layout of the integrated circuit based on the first layout and the standard cell layout and performing a color check on the via color layout based on design rules. The first layout having a first set of vias arranged in first rows and first columns. The standard cell layout having standard cells and a second set of vias arranged in the standard cells. The via color layout having a third set of vias. The third set of vias including a portion of the second set of vias and corresponding locations, and color of corresponding sub-set of vias.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Lin, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shih-Wei Peng, Wei-Chen Chien
  • Publication number: 20190147134
    Abstract: Implementations of the disclosure provide a method of fabricating an integrated circuit (IC). The method includes receiving an IC design layout; performing optical proximity correction (OPC) process to the IC design layout to produce a corrected IC design layout; and verifying the corrected IC design layout using a machine learning algorithm. The post OPC verification includes using the machine learning algorithm to identify one or more features of the corrected IC design layout; comparing the one or more identified features to a database comprising a plurality of features; and verifying the corrected IC design layout based on labels in the database associated with the plurality of features.
    Type: Application
    Filed: November 14, 2017
    Publication date: May 16, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chun Wang, Cheng Kun Tsai, Wen-Chun Huang, Wei-Chen Chien, Chi-Ping Liu
  • Publication number: 20190094710
    Abstract: Examples of optical proximity correction (OPC) based computational lithography techniques are disclosed herein. An exemplary method includes receiving an IC design layout that includes an IC feature, the IC feature specifying a mask feature for selectively exposing to radiation a portion of a photoresist disposed on a substrate; determining topographical information of an underlying layer disposed on the substrate between the photoresist and the substrate; performing an OPC process on the IC feature to generate a modified IC feature; and providing a modified IC design layout including the modified IC feature for fabricating a mask based on the modified IC design layout. The OPC process may use the topographical information of the underlying layer to compensate for an amount of radiation directed towards the portion of the photoresist so as to expose the portion of the photoresist to a target dosage of radiation.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 28, 2019
    Inventors: Hung-Chun Wang, Chi-Ping Liu, Cheng Kun Tsai, Wei-Chen Chien, Wen-Chun Huang
  • Publication number: 20180261727
    Abstract: The invention provides an LED including a first-type semiconductor layer, an emitting layer, a second-type semiconductor layer, a first electrode, a second electrode, a Bragg reflector structure, a conductive layer and insulation patterns. The first electrode and the second electrode are located on the same side of the Bragg reflector structure. The conductive layer is disposed between the Bragg reflector structure and the second-type semiconductor layer. The insulation patterns are disposed between the conductive layer and the second-type semiconductor layer. Each insulating layer has a first surface facing toward the second-type semiconductor layer, a second surface facing away from the second-type semiconductor layer, and an inclined surface. The inclined surface connects the first surface and the second surface and is inclined with respect to the first surface and the second surface.
    Type: Application
    Filed: May 16, 2018
    Publication date: September 13, 2018
    Applicant: Genesis Photonics Inc.
    Inventors: Yi-Ru Huang, Tung-Lin Chuang, Yan-Ting Lan, Sheng-Tsung Hsu, Chih-Ming Shen, Jing-En Huang, Teng-Hsien Lai, Hung-Chuan Mai, Kuan-Chieh Huang, Shao-Ying Ting, Cheng-Pin Chen, Wei-Chen Chien, Chih-Chin Cheng, Chih-Hung Tseng
  • Publication number: 20180248078
    Abstract: Provided is a light-emitting diode chip including a semiconductor device layer, a first electrode, a current-blocking layer, a current-spreading layer, and a second electrode. The semiconductor device layer includes a first-type doped semiconductor layer, a second-type doped semiconductor layer, and a light-emitting layer therebetween. The first electrode is electrically connected to the first-type doped semiconductor layer. The current-blocking layer is on the second-type doped semiconductor layer. The current-blocking layer is between the current-spreading layer and the second-type doped semiconductor layer. The second electrode is on the current-spreading layer and electrically connected to the second-type doped semiconductor layer. The current-blocking layer has a first surface facing the semiconductor device layer, a second surface back on to the semiconductor device layer, and a first inclined surface.
    Type: Application
    Filed: April 30, 2018
    Publication date: August 30, 2018
    Inventors: Yu-Chen Kuo, Teng-Hsien Lai, Kai-Shun Kang, Yan-Ting Lan, Jing-En Huang, Cheng-Pin Chen, Wei-Chen Chien, Chih-Chin Cheng, Chih-Hung Tseng
  • Publication number: 20180173090
    Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.
    Type: Application
    Filed: July 19, 2017
    Publication date: June 21, 2018
    Inventors: Hung-Chun Wang, Chi-Ping Liu, Feng-Ju Chang, Ching-Hsu Chang, Wen Hao Liu, Chia-Feng Yeh, Ming-Hui Chih, Cheng Kun Tsai, Wei-Chen Chien, Wen-Chun Huang, Yu-Po Tang
  • Publication number: 20180068050
    Abstract: A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes generating a first layout of the integrated circuit based on design criteria, generating a standard cell layout of the integrated circuit, generating a via color layout of the integrated circuit based on the first layout and the standard cell layout and performing a color check on the via color layout based on design rules. The first layout having a first set of vias arranged in first rows and first columns. The standard cell layout having standard cells and a second set of vias arranged in the standard cells. The via color layout having a third set of vias. The third set of vias including a portion of the second set of vias and corresponding locations, and color of corresponding sub-set of vias.
    Type: Application
    Filed: September 7, 2016
    Publication date: March 8, 2018
    Inventors: Wei-Cheng LIN, Chih-Liang CHEN, Chih-Ming LAI, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kam-Tou SIO, Ru-Gun LIU, Shih-Wei PENG, Wei-Chen CHIEN
  • Publication number: 20160329461
    Abstract: The invention provides an LED including a first-type semiconductor layer, an emitting layer, a second-type semiconductor layer, a first electrode, a second electrode, a Bragg reflector structure, a conductive layer and insulation patterns. The first electrode and the second electrode are located on the same side of the Bragg reflector structure. The conductive layer is disposed between the Bragg reflector structure and the second-type semiconductor layer. The insulation patterns are disposed between the conductive layer and the second-type semiconductor layer. Each insulating layer has a first surface facing toward the second-type semiconductor layer, a second surface facing away from the second-type semiconductor layer, and an inclined surface. The inclined surface connects the first surface and the second surface and is inclined with respect to the first surface and the second surface.
    Type: Application
    Filed: April 22, 2016
    Publication date: November 10, 2016
    Inventors: Yi-Ru Huang, Tung-Lin Chuang, Yan-Ting Lan, Sheng-Tsung Hsu, Chih-Ming Shen, Jing-En Huang, Teng-Hsien Lai, Hung-Chuan Mai, Kuan-Chieh Huang, Shao-Ying Ting, Cheng-Pin Chen, Wei-Chen Chien, Chih-Chin Cheng, Chih-Hung Tseng
  • Publication number: 20160315238
    Abstract: Provided is a light-emitting diode chip including a semiconductor device layer, a first electrode, a current-blocking layer, a current-spreading layer, and a second electrode. The semiconductor device layer includes a first-type doped semiconductor layer, a second-type doped semiconductor layer, and a light-emitting layer therebetween. The first electrode is electrically connected to the first-type doped semiconductor layer. The current-blocking layer is on the second-type doped semiconductor layer. The current-blocking layer is between the current-spreading layer and the second-type doped semiconductor layer. The second electrode is on the current-spreading layer and electrically connected to the second-type doped semiconductor layer. The current-blocking layer has a first surface facing the semiconductor device layer, a second surface back on to the semiconductor device layer, and a first inclined surface.
    Type: Application
    Filed: April 22, 2016
    Publication date: October 27, 2016
    Inventors: Yu-Chen Kuo, Teng-Hsien Lai, Kai-Shun Kang, Yan-Ting Lan, Jing-En Huang, Cheng-Pin Chen, Wei-Chen Chien, Chih-Chin Cheng, Chih-Hung Tseng
  • Patent number: 7721028
    Abstract: An improved KVM switch is provided which enables computers to be connected to the KVM switch by reduced numbers of cables. It also supports transmission of digital audio signals between the computers and the KVM switch. A single USB port is provided to transmit keyboard, mouse, speaker and microphone signals between the KVM switch and each computer. The improved KVM switch is provided with one or more USB hubs to separate the keyboard/mouse signals and the digital audio signals, and one or more audio codecs to convert the audio signals from a digital form to an analog form and vice versa.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: May 18, 2010
    Assignee: ATEN International Co., Ltd.
    Inventor: Wei-Chen Chien
  • Publication number: 20090198848
    Abstract: An improved KVM switch is provided which enables computers to be connected to the KVM switch by reduced numbers of cables. It also supports transmission of digital audio signals between the computers and the KVM switch. A single USB port is provided to transmit keyboard, mouse, speaker and microphone signals between the KVM switch and each computer. The improved KVM switch is provided with one or more USB hubs to separate the keyboard/mouse signals and the digital audio signals, and one or more audio codecs to convert the audio signals from a digital form to an analog form and vice versa.
    Type: Application
    Filed: February 4, 2008
    Publication date: August 6, 2009
    Applicant: ATEN INTERNATIONAL CO., LTD.
    Inventor: Wei-Chen Chien