Abstract: A method is provided for fabricating an interconnection structure. A first metal layer is formed over a semiconductor substrate. The first metal layer is patterned to form a first metal line and a second metal line. An interlayer dielectric layer is deposited over the first metal line and the second metal line, where the interlayer dielectric layer has a first air gap disposed between the first metal line and the second metal line. A via hole is formed in the interlayer dielectric layer, where the via hole exposes the first metal line. A metal via is formed in the via hole.

Abstract: A memory device includes a first lower epitaxial source/drain region adjacent a second lower epitaxial source/drain region; a first lower gate electrode adjacent a first side of the first lower epitaxial source/drain region; a second lower gate electrode adjacent a second side of the second lower epitaxial source/drain region, wherein the second side is opposite the first side; a dielectric layer under the first lower epitaxial source/drain region, the second lower epitaxial source/drain region, the first lower gate electrode, and the second lower gate electrode; a first butted contact within the dielectric layer, wherein the first butted contact electrically connects the first lower epitaxial source/drain region to the second lower gate electrode; and a second butted contact within the dielectric layer, wherein the second butted contact electrically connects the second lower epitaxial source/drain region to the first lower gate electrode.

Abstract: In an embodiment, a method may include forming a via hole in a dielectric layer, performing a directional etching process to enlarge one side of the via hole, and after the directional etching process, forming a trench hole in the dielectric layer, where the trench hole is above and spatially connected with the via hole, where the directional etching creates an asymmetrical profile having a first side width and a second side width measured from a center of the via hole, the second side width being greater than the first side width. The method may further include filling the via hole and the trench hole with a conductive material.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first interconnect layer over a substrate, the first interconnect layer including a first conductive feature and a second conductive feature, forming a patterned mask on the first interconnect layer, one or more openings in the patterned mask overlaying the second conductive feature, recessing the second conductive feature through the one or more openings in the patterned mask, and forming a second interconnect layer over the first interconnect layer. The second interconnect layer includes a first via in contact with the first conductive feature and a second via in contact with the second conductive feature.

Abstract: A memory structure is provided. The memory structure includes a first pull-up transistor in a first active region, a second pull-up transistor in a second active region parallel to and separated from the first active region, and an electrode overlapping the first and second active regions and configured to electrically connect a gate structure of the second pull-up transistor to a drain region of the first pull-up transistor. The electrode is formed in a metal layer closest to the first and second active regions.

Abstract: An interconnection structure includes a substrate, a first dielectric layer over the substrate, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, and a hyper via. The first dielectric layer is formed with a first metal trench. The second dielectric layer is formed with a metal plate and a connection via. The connection via interconnects the metal plate and the first metal trench. The hyper via penetrates the third dielectric layer and is connected to the metal plate. The hyper via is at least 1.5 times wider than the connection via.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate comprising a device region, a first interconnect layer disposed over the device region, and a second interconnect layer disposed over the first interconnect layer. The first interconnect layer includes first metal lines and second metal lines. A height of the first metal lines is greater than a height of the second metal lines. A thickness of the first interconnect layer is different from a thickness of the second interconnect layer.

Abstract: Embodiments of the present disclosure provide integrated circuit chips including via towers formed with stacks of conductive layers formed during fabrication of semiconductor devices and interconnect structures of the integrated circuit chips. The via towers may be connected to provide electrical power to subsequently stacked integrated circuit chips. The via towers according to the present disclosure reduce cost of fabrication because the via towers are fabricated without additional processing sequences. The via towers may be integrated in the circuit layout to form a low resistance power rail, therefore, improving performance.

Abstract: A semiconductor structure includes an interconnect structure including a first metallic pattern and a metal oxide layer. The first metallic pattern is disposed in a first opening of a dielectric layer and includes a first barrier layer lining the first opening and a first conductive layer over the first barrier layer. A top surface of the first conductive layer is between a top surface and a bottom surface of the dielectric layer. The metal oxide layer is on the top surface of the first conductive layer, and a top surface of the metal oxide layer is substantially leveled with the top surface of the dielectric layer.

Abstract: An interconnection structure includes a semiconductor substrate, an interlayer dielectric layer that is disposed over the semiconductor substrate, and a metal trench that is formed in the interlayer dielectric layer. The interlayer dielectric layer is formed with an air gap, and the metal trench is disposed over the air gap.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a conductive line over the semiconductor substrate. The conductive line has a barrier region surrounding an inner portion of the conductive line, and the barrier region has a greater dopant concentration than the inner portion. The semiconductor device structure also includes a conductive via on the conductive line. The semiconductor device structure further includes a dielectric layer over the semiconductor substrate. The dielectric layer surrounds the conductive line and the conductive via.

Abstract: An interconnection structure includes a semiconductor substrate that is formed with a first metal trench and a second metal trench, a first metal via, a second metal via, a third metal trench and a fourth metal trench. The first metal via is disposed over and connected to the first metal trench. The second metal via is disposed over and connected to the second metal trench. The third metal trench is disposed over and connected to the first metal via. The fourth metal trench that is disposed over and connected to the second metal via. A thickness of the third metal trench is different from a thickness of the fourth metal trench.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first dielectric layer, a first metal layer, a via, an air gap, an etching stop layer, a second dielectric layer, and a second metal layer. The first metal layer is embedded in the first dielectric layer. The first metal layer includes a first conductive line and a second conductive line. The via is disposed on the first conductive line. The air gap is located on the second conductive line. The sustaining layer covers the air gap. The etching stop layer is disposed on the sustaining layer. The second dielectric layer is disposed on the etching stop layer. The second metal layer is disposed on the second dielectric layer and connected to the via.

Abstract: A method of semiconductor fabrication includes forming a plurality of mandrel recesses in a mandrel layer over a hard mask layer, performing a first patterning process on a spacer layer that is deposited over the mandrel layer to form a first opening pattern, performing a second patterning process to etch portions of the mandrel layer to form a second opening pattern, performing a third patterning process to form a third opening pattern in the hard mask layer based on the first opening pattern and the second opening pattern, and forming, through the hard mask layer, metal lines that are in a semiconductor layer under the hard mask layer and that are arranged in a pattern which corresponds to the third opening pattern.

Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, and a barrier layer. The first conductive feature is disposed on the first dielectric layer, the second dielectric layer is disposed on the first dielectric layer and surrounds the sidewalls of the first conductive feature, the barrier layer is disposed between the first dielectric layer and the second dielectric layer and between the sidewalls of the first conductive feature and the second dielectric layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first low dielectric constant (low-k) layer, a first metal layer, a metal cap layer, a dielectric on dielectric (DoD) layer, an etch stop layer (ESL), a second low-k layer, a metal via and a second metal layer. The dielectric constant of the first low-k layer is less than 4. The first metal layer is embodied in the first low-k layer. The first low-k layer exposes the first metal layer. The metal cap layer is disposed on the first metal layer. The DoD layer is disposed on the first low-k layer. The etch stop layer is disposed on the metal cap layer and the DoD layer. The second low-k layer is disposed above the etch stop layer. The metal via is embodied in the second low-k layer and connected to the first metal layer.

Abstract: The present disclosure relates to an integrated chip that includes a substrate, a first metal line, and a hybrid metal line. The first metal line includes a first metal material and is within a first interlayer dielectric (ILD) layer over the substrate. The hybrid metal line is also within the first ILD layer. The hybrid metal line includes a pair of first metal segments that comprise the first metal material. The hybrid metal line further includes a second metal segment that comprises a second metal material that is different from the first metal material. The second metal segment is laterally between the pair of first metal segments.

Abstract: An interconnection structure includes a substrate, a first dielectric layer over the substrate, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, and a hyper via. The first dielectric layer is formed with a first metal trench. The second dielectric layer is formed with a metal plate and a connection via. The connection via interconnects the metal plate and the first metal trench. The hyper via penetrates the third dielectric layer and is connected to the metal plate. The hyper via is at least 1.5 times wider than the connection via.

Abstract: A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.

Abstract: A method for manufacturing a semiconductor structure includes: forming a patterned first layer which is made of a first electrically conductive material, and which includes first lines, second lines, and a connection portion disposed on a part of one of the first lines, the first lines having a height lower than a height of the second lines; forming a first via which is connected to an upper surface of the connection portion, the first via having a height above the connection portion; and forming a second via which is connected to an upper surface of one of the second lines, the second via having a height that is the same as the height of the first via above the connection portion.