Patents by Inventor Wei-Chen CHU
Wei-Chen CHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240085803Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
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Patent number: 11860550Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.Type: GrantFiled: July 19, 2022Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
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Publication number: 20230369096Abstract: A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Tai-I YANG, Wei-Chen CHU, Yung-Chih WANG, Chia-Tien WU, Hsin-Ping CHEN, Shau-Lin SHUE
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Publication number: 20230309296Abstract: A semiconductor device and a method of operating the same are provided. The semiconductor device includes a transistor and a fuse structure electrically connected to the transistor. The fuse structure includes a first fuse element, a second fuse element, and a fuse medium. The second fuse element at least partially overlaps the first fuse element. The fuse medium connects the first fuse element and the second fuse element. The fuse medium includes an electrically conductive material.Type: ApplicationFiled: June 1, 2023Publication date: September 28, 2023Inventors: HSIANG-WEI LIU, WEI-CHEN CHU, CHIA-TIEN WU
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Patent number: 11764106Abstract: A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.Type: GrantFiled: April 26, 2021Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Tai-I Yang, Wei-Chen Chu, Yung-Chih Wang, Chia-Tien Wu, Hsin-Ping Chen, Shau-Lin Shue
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Publication number: 20230282571Abstract: The present disclosure relates to an integrated chip that includes a substrate, a first metal line, and a hybrid metal line. The first metal line includes a first metal material and is within a first interlayer dielectric (ILD) layer over the substrate. The hybrid metal line is also within the first ILD layer. The hybrid metal line includes a pair of first metal segments that comprise the first metal material. The hybrid metal line further includes a second metal segment that comprises a second metal material that is different from the first metal material. The second metal segment is laterally between the pair of first metal segments.Type: ApplicationFiled: May 8, 2023Publication date: September 7, 2023Inventors: Pokuan Ho, Chia-Tien Wu, Hsin-Ping Chen, Wei-Chen Chu
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Publication number: 20230275018Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first interconnect layer over a substrate, the first interconnect layer including a first conductive feature and a second conductive feature, forming a patterned mask on the first interconnect layer, one or more openings in the patterned mask overlaying the second conductive feature, recessing the second conductive feature through the one or more openings in the patterned mask, and forming a second interconnect layer over the first interconnect layer. The second interconnect layer includes a first via in contact with the first conductive feature and a second via in contact with the second conductive feature.Type: ApplicationFiled: June 4, 2022Publication date: August 31, 2023Inventors: Chia-Tien Wu, Wei-Chen Chu, Yu-Chieh Liao, Hsin-Ping Chen
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Publication number: 20230262968Abstract: A semiconductor device and a method of operating the same are provided. The semiconductor device includes a transistor and a fuse structure electrically connected to the transistor. The fuse structure includes a first fuse element, a second fuse element, and a fuse medium. The second fuse element at least partially overlaps the first fuse element. The fuse medium connects the first fuse element and the second fuse element. The fuse medium includes an electrically conductive material.Type: ApplicationFiled: February 15, 2022Publication date: August 17, 2023Inventors: HSIANG-WEI LIU, WEI-CHEN CHU, CHIA-TIEN WU
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Patent number: 11729969Abstract: A semiconductor device and a method of operating the same are provided. The semiconductor device includes a transistor and a fuse structure electrically connected to the transistor. The fuse structure includes a first fuse element, a second fuse element, and a fuse medium. The second fuse element at least partially overlaps the first fuse element. The fuse medium connects the first fuse element and the second fuse element. The fuse medium includes an electrically conductive material.Type: GrantFiled: February 15, 2022Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsiang-Wei Liu, Wei-Chen Chu, Chia-Tien Wu
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Patent number: 11682618Abstract: The present disclosure relates to an integrated chip that includes a substrate, a first metal line, and a hybrid metal line. The first metal line includes a first metal material and is within a first interlayer dielectric (ILD) layer over the substrate. The hybrid metal line is also within the first ILD layer. The hybrid metal line includes a pair of first metal segments that comprise the first metal material. The hybrid metal line further includes a second metal segment that comprises a second metal material that is different from the first metal material. The second metal segment is laterally between the pair of first metal segments.Type: GrantFiled: March 25, 2021Date of Patent: June 20, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pokuan Ho, Chia-Tien Wu, Hsin-Ping Chen, Wei-Chen Chu
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Publication number: 20230067527Abstract: A semiconductor structure includes a substrate, a dielectric layer, a first conductive feature and a second conductive feature. The substrate includes a semiconductor device. The dielectric layer is disposed on the substrate. The first conductive feature is formed in the first dielectric layer. The second conductive feature penetrates the first conductive feature and the dielectric layer, and is electrically connected to the first conductive feature and the semiconductor device.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Chen CHU, Chia-Tien WU, Chia-Wei SU, Yu-Chieh LIAO, Chia-Chen LEE, Hsin-Ping CHEN, Shau-Lin SHUE
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Publication number: 20220359380Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a conductive line over the semiconductor substrate. The conductive line has a barrier region surrounding an inner portion of the conductive line, and the barrier region has a greater dopant concentration than the inner portion. The semiconductor device structure also includes a conductive via on the conductive line. The semiconductor device structure further includes a dielectric layer over the semiconductor substrate. The dielectric layer surrounds the conductive line and the conductive via.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tai-I YANG, Wei-Chen CHU, Yung-Hsu WU, Chung-Ju LEE
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Publication number: 20220350262Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.Type: ApplicationFiled: July 19, 2022Publication date: November 3, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I YANG, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
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Publication number: 20220310508Abstract: The present disclosure relates to an integrated chip that includes a substrate, a first metal line, and a hybrid metal line. The first metal line includes a first metal material and is within a first interlayer dielectric (ILD) layer over the substrate. The hybrid metal line is also within the first ILD layer. The hybrid metal line includes a pair of first metal segments that comprise the first metal material. The hybrid metal line further includes a second metal segment that comprises a second metal material that is different from the first metal material. The second metal segment is laterally between the pair of first metal segments.Type: ApplicationFiled: March 25, 2021Publication date: September 29, 2022Inventors: Pokuan Ho, Chia-Tien Wu, Hsin-Ping Chen, Wei-Chen Chu
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Patent number: 11422475Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.Type: GrantFiled: December 20, 2019Date of Patent: August 23, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
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Patent number: 11404367Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a conductive layer over a semiconductor substrate and forming a sacrificial layer over the conductive layer. The method also includes partially removing the sacrificial layer to form a first dummy element. The method further includes etching the conductive layer with the first dummy element as an etching mask to form a conductive line. In addition, the method includes partially removing the first dummy element to form a second dummy element over the conductive line. The method also includes forming a dielectric layer to surround the conductive line and the second dummy element and removing the second dummy element to form a via hole exposing the conductive line. The method further includes forming a conductive via in the via hole.Type: GrantFiled: July 13, 2020Date of Patent: August 2, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I Yang, Wei-Chen Chu, Yung-Hsu Wu, Chung-Ju Lee
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Publication number: 20210391211Abstract: The present disclosure provides an interconnect structure, including a first metal line, a second metal line spaced away from the first metal line, a conductive contact over the first metal line, including a first portion, a second portion over the first portion, wherein a bottom width of the second portion is greater than a top width of the first portion, wherein a shortest distance between the second portion and the second metal line is in a range from 50 Angstrom to 200 Angstrom, and a third portion over the second portion, wherein a bottom width of the third portion is greater than a top width of the second portion, the entire first portion and the entire second portion are under a coverage of a. vertical projection area of the third portion, a first layer, and a second layer over the first layer.Type: ApplicationFiled: August 27, 2021Publication date: December 16, 2021Inventors: HSIANG-WEI LIU, WEI-CHEN CHU, CHIA-TIEN WU, TAI-I YANG
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Patent number: 11183422Abstract: A semiconductor structure includes an integrated circuit, a first dielectric layer over the integrated circuit, an etch stop layer over the first dielectric layer, a barrier layer over the etch stop layer, a conductive layer over the barrier layer, and a void region vertically extending through the conductive layer, the barrier layer, and the etch stop layer. The void region has an upper portion, a middle portion below the upper portion, and a lower portion below the middle portion, the middle portion. The middle portion is narrower than the upper portion and the lower portion.Type: GrantFiled: October 7, 2020Date of Patent: November 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tai-I Yang, Wei-Chen Chu, Hsin-Ping Chen, Chih-Wei Lu, Chung-Ju Lee
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Patent number: 11107725Abstract: The present disclosure provides an interconnect structure, including a first metal line, a conductive contact over the first metal line, including a first portion, a second portion over the first portion, wherein a bottom width of the second portion is greater than a top width of the first portion, and a third portion over the second portion, wherein a bottom width of the third portion is greater than a top width of the second portion, a sacrificial bilayer, including a first sacrificial layer, wherein a first portion of the first sacrificial layer is under a coverage of a vertical projection area of the first portion of the conductive contact, and a second sacrificial layer over the first sacrificial layer, and a dielectric layer over a top surface of the second sacrificial layer.Type: GrantFiled: September 20, 2020Date of Patent: August 31, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsiang-Wei Liu, Wei-Chen Chu, Chia-Tien Wu, Tai-I Yang
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Patent number: 11088020Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a conductive feature in a first dielectric layer. The semiconductor device structure also includes an etching stop layer over the first dielectric layer and a second dielectric layer over the etching stop layer. The semiconductor device structure further includes a conductive via in the etching stop layer and the second dielectric layer. In addition, the semiconductor device structure includes a conductive line over the conductive via. The semiconductor device structure also includes a first barrier liner covering the bottom surface of the conductive line. The semiconductor device structure further includes a second barrier liner surrounding sidewalls of the conductive line and the conductive via. The conductive line and the conductive via are confined in the first barrier liner and the second barrier liner.Type: GrantFiled: August 30, 2017Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I Yang, Wei-Chen Chu, Li-Lin Su, Shin-Yi Yang, Cheng-Chi Chuang, Hsin-Ping Chen