Patents by Inventor Wei-Chen CHU

Wei-Chen CHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149437
    Abstract: An interconnection structure includes a semiconductor substrate that is formed with a first metal trench and a second metal trench, a first metal via, a second metal via, a third metal trench and a fourth metal trench. The first metal via is disposed over and connected to the first metal trench. The second metal via is disposed over and connected to the second metal trench. The third metal trench is disposed over and connected to the first metal via. The fourth metal trench that is disposed over and connected to the second metal via. A thickness of the third metal trench is different from a thickness of the fourth metal trench.
    Type: Application
    Filed: November 6, 2023
    Publication date: May 8, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Chen CHU, Chia-Chen LEE, Chia-Tien WU
  • Publication number: 20250140683
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first dielectric layer, a first metal layer, a via, an air gap, an etching stop layer, a second dielectric layer, and a second metal layer. The first metal layer is embedded in the first dielectric layer. The first metal layer includes a first conductive line and a second conductive line. The via is disposed on the first conductive line. The air gap is located on the second conductive line. The sustaining layer covers the air gap. The etching stop layer is disposed on the sustaining layer. The second dielectric layer is disposed on the etching stop layer. The second metal layer is disposed on the second dielectric layer and connected to the via.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 1, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Pu CHOU, Chia-Tien WU, Hsin-Ping CHEN, Wei-Chen CHU
  • Publication number: 20250125148
    Abstract: A method of semiconductor fabrication includes forming a plurality of mandrel recesses in a mandrel layer over a hard mask layer, performing a first patterning process on a spacer layer that is deposited over the mandrel layer to form a first opening pattern, performing a second patterning process to etch portions of the mandrel layer to form a second opening pattern, performing a third patterning process to form a third opening pattern in the hard mask layer based on the first opening pattern and the second opening pattern, and forming, through the hard mask layer, metal lines that are in a semiconductor layer under the hard mask layer and that are arranged in a pattern which corresponds to the third opening pattern.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 17, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chen LEE, Chia-Tien WU, Wei-Chen CHU, Hsi-Wen TIEN, Wei-Cheng TZENG, Ching-Yu HUANG, Wei-Cheng LIN, Ken-Hsien HSIEH
  • Publication number: 20250118598
    Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, and a barrier layer. The first conductive feature is disposed on the first dielectric layer, the second dielectric layer is disposed on the first dielectric layer and surrounds the sidewalls of the first conductive feature, the barrier layer is disposed between the first dielectric layer and the second dielectric layer and between the sidewalls of the first conductive feature and the second dielectric layer.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Shao-Kuan LEE, Kuang-Wei YANG, Gary HSU WEI LIU, Yen-Ju WU, Jing-Ting SU, Hsin-Yen HUANG, Hsiao-Kang CHANG, Wei-Chen CHU, Shu-Yun KU, Chia-Tien WU, Ming-Han LEE, Hsin-Ping CHEN
  • Publication number: 20250112088
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first low dielectric constant (low-k) layer, a first metal layer, a metal cap layer, a dielectric on dielectric (DoD) layer, an etch stop layer (ESL), a second low-k layer, a metal via and a second metal layer. The dielectric constant of the first low-k layer is less than 4. The first metal layer is embodied in the first low-k layer. The first low-k layer exposes the first metal layer. The metal cap layer is disposed on the first metal layer. The DoD layer is disposed on the first low-k layer. The etch stop layer is disposed on the metal cap layer and the DoD layer. The second low-k layer is disposed above the etch stop layer. The metal via is embodied in the second low-k layer and connected to the first metal layer.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chin LEE, Yen Ju WU, Shao-Kuan LEE, Kuang-Wei YANG, Hsin-Yen HUANG, Jing Ting SU, Kai-Fang CHENG, Hsiao-Kang CHANG, Wei-Chen CHU, Shu-Yun KU, Chia-Tien WU, Ming-Han LEE, Hsin-Ping CHEN
  • Publication number: 20250079295
    Abstract: An interconnection structure includes a substrate, a first dielectric layer over the substrate, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, and a hyper via. The first dielectric layer is formed with a first metal trench. The second dielectric layer is formed with a metal plate and a connection via. The connection via interconnects the metal plate and the first metal trench. The hyper via penetrates the third dielectric layer and is connected to the metal plate. The hyper via is at least 1.5 times wider than the connection via.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 6, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chen LEE, Chia-Tien WU, Wei-Chen CHU
  • Publication number: 20250079298
    Abstract: The present disclosure relates to an integrated chip that includes a substrate, a first metal line, and a hybrid metal line. The first metal line includes a first metal material and is within a first interlayer dielectric (ILD) layer over the substrate. The hybrid metal line is also within the first ILD layer. The hybrid metal line includes a pair of first metal segments that comprise the first metal material. The hybrid metal line further includes a second metal segment that comprises a second metal material that is different from the first metal material. The second metal segment is laterally between the pair of first metal segments.
    Type: Application
    Filed: November 19, 2024
    Publication date: March 6, 2025
    Inventors: Pokuan Ho, Chia-Tien Wu, Hsin-Ping Chen, Wei-Chen Chu
  • Patent number: 12230534
    Abstract: A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Tai-I Yang, Wei-Chen Chu, Yung-Chih Wang, Chia-Tien Wu, Hsin-Ping Chen, Shau-Lin Shue
  • Publication number: 20250054811
    Abstract: A method for manufacturing a semiconductor structure includes: forming a patterned first layer which is made of a first electrically conductive material, and which includes first lines, second lines, and a connection portion disposed on a part of one of the first lines, the first lines having a height lower than a height of the second lines; forming a first via which is connected to an upper surface of the connection portion, the first via having a height above the connection portion; and forming a second via which is connected to an upper surface of one of the second lines, the second via having a height that is the same as the height of the first via above the connection portion.
    Type: Application
    Filed: August 7, 2023
    Publication date: February 13, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Chen CHU, Chia-Tien WU, Chuan-Pu CHOU, Hsin-Ping CHEN
  • Patent number: 12183671
    Abstract: The present disclosure relates to an integrated chip that includes a substrate, a first metal line, and a hybrid metal line. The first metal line includes a first metal material and is within a first interlayer dielectric (ILD) layer over the substrate. The hybrid metal line is also within the first ILD layer. The hybrid metal line includes a pair of first metal segments that comprise the first metal material. The hybrid metal line further includes a second metal segment that comprises a second metal material that is different from the first metal material. The second metal segment is laterally between the pair of first metal segments.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: December 31, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pokuan Ho, Chia-Tien Wu, Hsin-Ping Chen, Wei-Chen Chu
  • Publication number: 20240379537
    Abstract: A semiconductor structure includes a substrate, a dielectric layer, a first conductive feature and a second conductive feature. The substrate includes a semiconductor device. The dielectric layer is disposed on the substrate. The first conductive feature is formed in the first dielectric layer. The second conductive feature penetrates the first conductive feature and the dielectric layer, and is electrically connected to the first conductive feature and the semiconductor device.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Chen CHU, Chia-Tien WU, Chia-Wei SU, Yu-Chieh LIAO, Chia-Chen LEE, Hsin-Ping CHEN, Shau-Lin SHUE
  • Patent number: 12094816
    Abstract: A semiconductor structure includes a substrate, a dielectric layer, a first conductive feature and a second conductive feature. The substrate includes a semiconductor device. The dielectric layer is disposed on the substrate. The first conductive feature is formed in the first dielectric layer. The second conductive feature penetrates the first conductive feature and the dielectric layer, and is electrically connected to the first conductive feature and the semiconductor device.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Chen Chu, Chia-Tien Wu, Chia-Wei Su, Yu-Chieh Liao, Chia-Chen Lee, Hsin-Ping Chen, Shau-Lin Shue
  • Patent number: 12058852
    Abstract: A semiconductor device and a method of operating the same are provided. The semiconductor device includes a transistor and a fuse structure electrically connected to the transistor. The fuse structure includes a first fuse element, a second fuse element, and a fuse medium. The second fuse element at least partially overlaps the first fuse element. The fuse medium connects the first fuse element and the second fuse element. The fuse medium includes an electrically conductive material.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsiang-Wei Liu, Wei-Chen Chu, Chia-Tien Wu
  • Patent number: 12002709
    Abstract: The present disclosure provides an interconnect structure, including a first metal line, a second metal line spaced away from the first metal line, a conductive contact over the first metal line, including a first portion, a second portion over the first portion, wherein a bottom width of the second portion is greater than a top width of the first portion, wherein a shortest distance between the second portion and the second metal line is in a range from 50 Angstrom to 200 Angstrom, and a third portion over the second portion, wherein a bottom width of the third portion is greater than a top width of the second portion, the entire first portion and the entire second portion are under a coverage of a vertical projection area of the third portion, a first layer, and a second layer over the first layer.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsiang-Wei Liu, Wei-Chen Chu, Chia-Tien Wu, Tai-I Yang
  • Publication number: 20240085803
    Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
  • Patent number: 11860550
    Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
  • Publication number: 20230369096
    Abstract: A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Inventors: Tai-I YANG, Wei-Chen CHU, Yung-Chih WANG, Chia-Tien WU, Hsin-Ping CHEN, Shau-Lin SHUE
  • Publication number: 20230309296
    Abstract: A semiconductor device and a method of operating the same are provided. The semiconductor device includes a transistor and a fuse structure electrically connected to the transistor. The fuse structure includes a first fuse element, a second fuse element, and a fuse medium. The second fuse element at least partially overlaps the first fuse element. The fuse medium connects the first fuse element and the second fuse element. The fuse medium includes an electrically conductive material.
    Type: Application
    Filed: June 1, 2023
    Publication date: September 28, 2023
    Inventors: HSIANG-WEI LIU, WEI-CHEN CHU, CHIA-TIEN WU
  • Patent number: 11764106
    Abstract: A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: September 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tai-I Yang, Wei-Chen Chu, Yung-Chih Wang, Chia-Tien Wu, Hsin-Ping Chen, Shau-Lin Shue
  • Publication number: 20230282571
    Abstract: The present disclosure relates to an integrated chip that includes a substrate, a first metal line, and a hybrid metal line. The first metal line includes a first metal material and is within a first interlayer dielectric (ILD) layer over the substrate. The hybrid metal line is also within the first ILD layer. The hybrid metal line includes a pair of first metal segments that comprise the first metal material. The hybrid metal line further includes a second metal segment that comprises a second metal material that is different from the first metal material. The second metal segment is laterally between the pair of first metal segments.
    Type: Application
    Filed: May 8, 2023
    Publication date: September 7, 2023
    Inventors: Pokuan Ho, Chia-Tien Wu, Hsin-Ping Chen, Wei-Chen Chu