Patents by Inventor Wei-Chen Teo

Wei-Chen Teo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090172256
    Abstract: A data writing method for a block of a multi level cell NAND flash memory including upper page addresses and lower page addresses is provided, wherein a writing speed at the lower page addresses is higher than that at the upper page addresses. The data writing method includes receiving a writing command and determining whether an address to be written with new data in the writing command is the upper page address of the block. The method also includes copying old data previously recorded on the lower page addresses of the block as an old data backup when the address to be written in the writing command is the upper page address of the block and then writing the new data to the address to be written. Thus, old data may be protected while writing data to the upper page address of the multi level cell NAND flash memory.
    Type: Application
    Filed: March 12, 2008
    Publication date: July 2, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chien-Hua Chu, Wei-Chen Teo