Patents by Inventor Wei-Chen YANG
Wei-Chen YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250185273Abstract: A high electron mobility transistor includes a semiconductor structure, a stepped trench, an electrode, and a gate. The semiconductor structure includes a barrier layer and a channel layer. The barrier layer is disposed on the channel layer. A two-dimensional electron gas is formed at an interface between the channel layer and the barrier layer. The stepped trench is disposed in the semiconductor structure. The electrode is disposed in the stepped trench. The gate is disposed on the barrier layer. The stepped trench has a first width and a second width. The first width is greater than the second width.Type: ApplicationFiled: November 5, 2024Publication date: June 5, 2025Applicant: HiPer Semiconductor Inc.Inventors: WEI-CHEN YANG, WEI-CHIH HO
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Publication number: 20250185272Abstract: A semiconductor structure of a high electron mobility transistor includes a channel layer, a barrier layer, a gate, a n-type material structure, and a metal electrode. The barrier layer is formed on the channel layer. A two-dimensional electron gas is formed in the channel layer along an interface between the channel layer and the barrier layer. The gate is formed on the barrier layer. The n-type material structure is in contact with the barrier layer. The metal electrode is a drain or a source and is disposed on a side of the gate.Type: ApplicationFiled: November 5, 2024Publication date: June 5, 2025Applicant: HiPer Semiconductor Inc.Inventors: WEI-CHEN YANG, WEI-CHIH HO
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Publication number: 20250169125Abstract: A high electron mobility transistor includes a substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer. The buffer layer includes a first buffer region, a second buffer region and a third buffer region. The first buffer region includes a first III-nitride stacked layer disposed on the nucleation layer and a second III-nitride stacked layer disposed on the first III-nitride stacked layer. The second buffer region is doped with carbon and iron. The third buffer region is doped with carbon and iron and has a carbon concentration greater than an iron concentration of the third buffer region. The second III-nitride stacked layer is doped with carbon and iron and has a carbon concentration greater than an iron concentration of the second III-nitride stacked layer.Type: ApplicationFiled: October 22, 2024Publication date: May 22, 2025Applicant: HiPer Semiconductor Inc.Inventors: PO-JUNG LIN, WEI-CHEN YANG
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Publication number: 20240405080Abstract: A high electron mobility transistor (HEMT) includes a GaN epi-layer, a first passivation layer, a source electrode metal, a drain electrode metal, a gate electrode metal, and a field plate. The first passivation layer is deposited on the GaN epi-layer. The source electrode metal, the drain electrode metal, and the gate electrode are recessed into the first passivation layer and deposited on the GaN epi-layer. The source electrode metal has a source field plate with a source field plate length Lsf. The drain electrode metal has a drain field plate with a drain field plate length Ldf, wherein Ldf>Lsf. The gate electrode is situated between the source electrode metal and the drain electrode metal. The field plate is situated between the gate electrode and the drain electrode metal.Type: ApplicationFiled: November 6, 2023Publication date: December 5, 2024Inventors: YAN LAI, WEI-CHEN YANG
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Publication number: 20240379836Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a dielectric material layer is disposed on the gate stack; and a field plate disposed on the dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure.Type: ApplicationFiled: July 25, 2024Publication date: November 14, 2024Inventors: Wei Wang, Wei-Chen Yang, Yao-Chung Chang, Ru-Yi Su, Yen-Ku Lin, Chuan-Wei Tsou, Chun Lin Tsai
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Publication number: 20240213334Abstract: A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor has a GaN epi-layer, a source ohmic contact, a drain ohmic contact, a gate structure, a first metal electrode contact and a first passivation layer. The source ohmic contact and the drain ohmic contact are disposed on the epi-layer. The gate structure is disposed on the epi-layer and between the source ohmic contact and the drain ohmic contact. The first metal electrode contact is disposed above the gate structure. The first passivation layer is sandwiched between the first metal electrode contact and the gate structure.Type: ApplicationFiled: September 13, 2023Publication date: June 27, 2024Inventors: YAN LAI, WEI-CHEN YANG
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Publication number: 20240145554Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.Type: ApplicationFiled: January 11, 2024Publication date: May 2, 2024Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
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Patent number: 11908905Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.Type: GrantFiled: July 18, 2022Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
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Patent number: 11848376Abstract: A high electron mobility transistor (HEMT) includes a GaN epi-layer, a first passivation layer, a source electrode metal, a drain electrode metal, a gate electrode metal, and a field plate. The first passivation layer is deposited on the GaN epi-layer. The source electrode metal, the drain electrode metal, and the gate electrode are recessed into the first passivation layer and deposited on the GaN epi-layer. The source electrode metal has a source field plate with a source field plate length Lsf. The drain electrode metal has a drain field plate with a drain field plate length Ldf, wherein Ldf>Lsf. The gate electrode is situated between the source electrode metal and the drain electrode metal. The field plate is situated between the gate electrode and the drain electrode metal.Type: GrantFiled: June 1, 2023Date of Patent: December 19, 2023Assignee: HIPER SEMICONDUCTOR INC.Inventors: Yan Lai, Wei-Chen Yang
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Patent number: 11799000Abstract: A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor has a GaN epi-layer, a source ohmic contact, a drain ohmic contact, a gate structure, a first metal electrode contact and a first passivation layer. The source ohmic contact and the drain ohmic contact are disposed on the epi-layer. The gate structure is disposed on the epi-layer and between the source ohmic contact and the drain ohmic contact. The first metal electrode contact is disposed above the gate structure. The first passivation layer is sandwiched between the first metal electrode contact and the gate structure.Type: GrantFiled: December 21, 2022Date of Patent: October 24, 2023Assignee: HIPER SEMICONDUCTOR INC.Inventors: Yan Lai, Wei-Chen Yang
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Publication number: 20220352325Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.Type: ApplicationFiled: July 18, 2022Publication date: November 3, 2022Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
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Patent number: 11450749Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a buffer layer disposed between an active layer and a substrate. The active layer overlies the substrate. The substrate and the buffer layer include a plurality of pillar structures that extend vertically from a bottom surface of the active layer in a direction away from the active layer. A top electrode overlies an upper surface of the active layer. A bottom electrode underlies the substrate. The bottom electrode includes a conductive body and a plurality of conductive structures that respectively extend continuously from the conductive body, along sidewalls of the pillar structures, to a lower surface of the active layer.Type: GrantFiled: May 27, 2020Date of Patent: September 20, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
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Publication number: 20220037518Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a dielectric material layer is disposed on the gate stack; and a field plate disposed on the dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure.Type: ApplicationFiled: June 9, 2021Publication date: February 3, 2022Inventors: Wei Wang, Wei-Chen Yang, Yao-Chung Chang, Ru-Yi Su, Yen-Ku Lin, Chuan-Wei Tsou, Chun Lin Tsai
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Publication number: 20210376090Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a buffer layer disposed between an active layer and a substrate. The active layer overlies the substrate. The substrate and the buffer layer include a plurality of pillar structures that extend vertically from a bottom surface of the active layer in a direction away from the active layer. A top electrode overlies an upper surface of the active layer. A bottom electrode underlies the substrate. The bottom electrode includes a conductive body and a plurality of conductive structures that respectively extend continuously from the conductive body, along sidewalls of the pillar structures, to a lower surface of the active layer.Type: ApplicationFiled: May 27, 2020Publication date: December 2, 2021Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
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Publication number: 20170207085Abstract: A horizontal semiconductor device includes an electrically conductive substrate having a first surface, a buffer layer disposed on the first surface of the substrate, an epitaxial unit disposed on the buffer layer opposite to the substrate, a first electrode unit disposed on the epitaxial unit, and a second electrode unit. The substrate has an exposed region that is exposed from the buffer layer and the epitaxial unit. The second electrode unit includes a first conductive member disposed on the epitaxial unit and spaced apart from the first electrode unit, and a second conductive member extending from the first conductive member to the exposed region.Type: ApplicationFiled: June 21, 2016Publication date: July 20, 2017Applicant: National Tsing Hua UniversityInventors: Chih-Fang HUANG, Keh-Yung CHENG, Wei-Chen YANG, Ting-Fu CHANG, Po-Ju CHU, Jian-Lin LIN, Ya-Chu LIAO, Hsin-Ying TSENG
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Patent number: 9502602Abstract: A structure of high electron mobility light emitting transistor comprises a substrate, a HEMT region disposed on the substrate, and a gallium nitride LED (GaN-LED) region disposed on the substrate. A two-dimensional electron gas layer is present in each of the HEMI region and the LED region, and the HEMT region is coupled to the LED region through the two-dimensional electron gas layer.Type: GrantFiled: December 31, 2014Date of Patent: November 22, 2016Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Chih-Fang Huang, Yi-Chen Li, Ting-Fu Chang, Keh-Yung Cheng, Yu-Li Wang, Chun-Hung Wu, Wei-Chen Yang, Shao-Yen Chiu
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Publication number: 20160190384Abstract: A structure of high electron mobility light emitting transistor comprises a substrate, a HEMT region disposed on the substrate, and a gallium nitride LED (GaN-LED) region disposed on the substrate. A two-dimensional electron gas layer is present in each of the HEMI region and the LED region, and the HEMT region is coupled to the LED region through the two-dimensional electron gas layer.Type: ApplicationFiled: December 31, 2014Publication date: June 30, 2016Inventors: Chih-Fang HUANG, Yi-Chen LI, Ting-Fu CHANG, Keh-Yung CHENG, Yu-Li WANG, Chun-Hung WU, Wei-Chen YANG, Shao-Yen CHIU
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Patent number: 9218965Abstract: By using a nano-scale patterning process, a dislocation defect density of a GaN epitaxy layer can be further reduced. This is because the nano-scale epitaxy structure dimension is advantageous to the reduction of the strain energy accumulated by mismatched lattices, thereby decreasing the possibility of generating defects. It is verified that the nano-scale patterning process can effectively decrease the dislocation defect density of the GaN epitaxial layer on a sapphire substrate. Considering uniformity and reproducibility on the application of the large-size wafer, the invention has utilized the soft mask NIL patterning technology to successfully implement the uniform deposition and position control of the InAs quantum dot on a GaAs substrate. This further utilizes the NIL technology in conjunction with dry-etching to perform the nano-scale patterning on a heterogeneous substrate, such as Si, sapphire or the like.Type: GrantFiled: March 28, 2014Date of Patent: December 22, 2015Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Keh-Yung Cheng, Yu-Li Wang, Wei-Chen Yang, Shao-Yen Chiu
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Publication number: 20150279656Abstract: By using a nano-scale patterning process, a dislocation defect density of a GaN epitaxy layer can be further reduced. This is because the nano-scale epitaxy structure dimension is advantageous to the reduction of the strain energy accumulated by mismatched lattices, thereby decreasing the possibility of generating defects. It is verified that the nano-scale patterning process can effectively decrease the dislocation defect density of the GaN epitaxial layer on a sapphire substrate. Considering uniformity and reproducibility on the application of the large-size wafer, the invention has utilized the soft mask NIL patterning technology to successfully implement the uniform deposition and position control of the InAs quantum dot on a GaAs substrate. This further utilizes the NIL technology in conjunction with dry-etching to perform the nano-scale patterning on a heterogeneous substrate, such as Si, sapphire or the like.Type: ApplicationFiled: March 28, 2014Publication date: October 1, 2015Applicant: National Tsing Hua UniversityInventors: Keh-Yung CHENG, Yu-Li WANG, Wei-Chen YANG, Shao-Yen CHIU