Abstract: A device includes a first transistor layer comprising a first gate electrode and a second transistor layer comprising a second gate electrode that is stacked with the first transistor layer. n intermetal structure comprising a conductive line is disposed between the first transistor layer and the second transistor layer. A first gate contact extends along a sidewall of the first gate electrode from a top surface of the first gate electrode to the conductive line 48G. A second gate contact extends along a sidewall of the second gate electrode from a top surface of the second gate electrode to the conductive line. The first gate electrode is electrically connected to the second gate electrode by the first gate contact, the second gate contact, and the conductive line.

Abstract: An IC structure includes first and second complementary field-effect transistors (CFETs) positioned in a semiconductor wafer, each of the first and second CFETs including a gate structure extending in a first direction, an n-type channel extending through the gate structure in a second direction perpendicular to the first direction, and a p-type channel extending through the gate structure in the second direction and aligned with the n-type channel in a third direction perpendicular to each of the first and second directions. A metal line extends in the first direction, is aligned with each of the first and second CFETs in the third direction, and is configured to distribute a power supply or reference voltage to each of the first and second CFETs. The metal line is a metal line closest to each of the first and second CFETs along the third direction and extending in the first direction.

Abstract: A device includes: an active region extending in a first direction; a first metal-to-S/D (MD) contact structure extending in a perpendicular second direction, and over and coupled to the active region; a first layer of metallization over the first MD contact structure and having M_1st segments extending in the first direction and each having a substantially same width relative to the second direction, the M_1st segments including M_1st routing segments, and an M_1st power grid (PG) segment having a portion over and coupled to the first MD contact structure; a second layer of metallization over the first layer of metallization and having M_2nd segments that extend in the second direction and include an M_2nd PG rail configured for a first reference voltage, a portion thereof being over and coupled to the M_1st PG segment. the M_2nd PG rail extending across multiple cell regions.

Abstract: A method (of forming a semiconductor device) including forming cell regions (in alternating first and second rows having first and second heights) including forming a majority of the cell regions in the first rows including: limiting a height of the majority of the cell regions to be single-row cell regions that span corresponding single one of the first rows but do not extend therebeyond; and forming a minority of the cell regions correspondingly in at least the first rows including reducing widths of the multi-row cell regions to be smaller than comparable single-row cell regions; and expanding heights of the minority of the cell regions to be multi-row cell regions, each of the multi-row cell regions spanning a corresponding single first row and at least a corresponding second row such that cell region densities of the second rows are at least about forty percent.

Abstract: An integrated circuit (IC) device includes a complementary field-effect transistor (CFET) device, a power rail at a first side of the CFET device, and a conductor at a second side of the CFET device. The CFET device includes a local interconnect. The first side is one of a front side and a back side of the CFET device. The second side is the other of the front side and the back side of the CFET device. The local interconnect of the CFET device electrically couples the power rail to the conductor.

Abstract: A method includes forming a multi-layer stack comprising dummy layers and semiconductor layers located alternatingly, and forming a plurality of dummy gate stacks on sidewalls and a top surface of the multi-layer stack. Two of the plurality of dummy gate stacks are immediately neighboring each other, and have a space in between. A first source/drain region and a second source/drain region are formed in the multi-layer stack, with the second source/drain region overlapping the first source/drain region. The method further includes replacing the plurality of dummy gate stacks with a plurality of replacement gate stacks, replacing a first one of the plurality of replacement gate stacks with a first dielectric isolation region, forming a deep contact plug in the space, forming a front-side via over the deep contact plug, and forming a back-side via under the deep contact plug, wherein the front-side via is electrically connected to the back-side via through the deep contact plug.

Abstract: A semiconductor device includes a first transistor having a first fin, wherein a base of the first fin is surrounded by a first dielectric material, the first fin having a first fin height measured from the top surface of the first dielectric material to a top surface of the first fin; and a second transistor having a second fin, wherein a base of the second fin is surrounded by a second dielectric material, the second fin having a second fin height measured from a top surface of the second dielectric material to a top surface of the second fin, wherein the first fin height is different from the second fin height.

Abstract: An integrated circuit includes a first pair of power rails and a second pair of power rails that are disposed in a first layer, conductive lines disposed in a second layer above the first layer, and a first active area disposed in a third layer above the second layer. The first active area is arranged to overlap the first pair of power rails. The first active area is coupled to the first pair of power rails through a first line of the conductive lines and a first group of vias, and the first active area is coupled to the second pair of power rails through at least one second line of the conductive lines and a second group of vias different from the first group of vias.

Abstract: An integrated circuit is provided, including a first cell. The first cell includes a first pair of active regions, at least one first gate, two first conductive segments, and a first interconnect structure. The first pair of active regions extends in a first direction and stacked on each other. The at least one first gate extends in a second direction different from the first direction, and is arranged across the first pair of active regions, to form at least one first pair of devices that are stacked on each other. The first conductive segments are coupled to the first pair of active regions respectively. The first interconnect structure is coupled to at least one of a first via or one of the two first conductive segments.

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, a first active region disposed on the substrate, a first gate structure disposed on the first active region, and a second gate structure disposed on the first active region and spaced apart from the first gate structure. The first active region includes a first portion and a second portion, the first portion of the first active region and the second portion of the first active region collectively specify a first stair profile. The first stair profile is located between the first gate structure and the second gate structure from a top view.

Abstract: A method is provided, including following operations: identifying a first contact via, a second contact via, or a combination thereof in a first standard cell, wherein the first contact via is coupled between a first active region and a first conductive line on a first side, and the second contact via is coupled between a second active region and a second conductive line on a second side; calculating a first cell height according to a first width of the first and second active regions, and calculating a second cell height according to a second width of the first and second active regions; calculating multiple first available cell heights based on a ratio between the first and second cell heights; generating layout designs of multiple first cells; and manufacturing at least first one element in the integrated circuit based on the layout designs of the first cells.

Abstract: A method is provided, including following operations: obtaining information on gate pitch and a ratio between the gate pitch and a first metal line pitch; comparing a preset metal line end spacing with a second metal line pitch, of multiple metal traces, and a spacing between a metal line layer and a power rail layer; in response to the comparison, defining multiple first metal line patterns overlapping multiple first gate patterns and defining multiple second metal line patterns disposed between two adjacent gate patterns in multiple second gate patterns; placing the first metal line patterns in a first row in a floorplan of an integrated circuit layout design and the second metal line patterns in a second row, adjacent the first row; and manufacturing at least one element in an integrated circuit based on the integrated circuit layout design.

Abstract: A semiconductor device includes a first transistor, a second transistor, a third transistor, and a contact. The first transistor includes a first source/drain (S/D), a second S/D, and a first gate between the first S/D and the second S/D. The first transistor and the second transistor are stacked over the third transistor. The contact covers the second S/D of the first transistor. The contact is electrically connected to the second transistor and electrically isolated from the second S/D.

Abstract: A device including first nanosheet structures each including a first number of nanosheets, second nanosheet structures each including a second number of nanosheets that is different than the first number of nanosheets, and a plurality of rows including first rows and second rows. Where each of the first nanosheet structures is in a respective one of the first rows, each of the second nanosheet structures is in a respective one of the second rows, at least two of the first rows are adjacent one another, and at least two of the second rows are adjacent one another.

Abstract: A semiconductor device includes first, second, and third conductive regions and first and second active regions. The first conductive region has a first width and extends along a first direction. The second conductive region has a second width and extends along the first direction. The first width is greater than the second width. The first active region has a third width and extends along the first direction. The second active region has a fourth width and extends along the first direction. The third width is less than the fourth width. The third conductive region extends along a second direction and is electrically connected to the first conductive region. The second direction is different from the first direction. The first and second active regions are neighboring active regions.