Abstract: A semiconductor device and method of manufacturing the device that includes a capacitive micromachined ultrasonic transducer (CMUT). The CMUT includes an integrated circuit substrate, and a sensing electrode positioned on the integrated substrate. The sensing electrode includes a sidewall that forms a wall of an isolation trench adjacent to the sensing electrode, and is patterned before covering dielectric layers are deposited. After patterning of the sensing electrode, one or more dielectric layers are patterned, with one dielectric layer patterned on the sensing electrode and sidewall, and which has a thickness corresponding to the surface roughness of the sensing electrode. The CMUT further includes a membrane positioned above the sensing electrode forming a cavity therein.

Abstract: The present disclosure provides an immersion cooling system for a server cabinet including a plurality of server boxes, a cooling tank and a plurality of liquid connecting pipes. Each server box includes an electronic device immersed in the cooling liquid, and the electronic device generates a thermal energy so that part of the cooling liquid evaporates into a hot vapor. The cooling tank is connected to the plurality of server boxes and includes a condenser and a storage part. The condenser is connected to each server box and condenses the hot vapor to form the cooling liquid. The storage part storages the cooling liquid from the condenser. Two ends of the liquid connecting pipe is connected to the storage part and the server box respectively. The cooling liquid in the storage part and the cooling liquid of each server box are maintained in a same liquid level.

Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.

Abstract: A network communication apparatus, includes a dispatch device, a first core group with several parallel core units and a second core group with at least one serial core unit. The dispatch device receives several packets contained in several first packet flows, and configured to dispatch several meta data to the parallel core units through several first data flows, and the meta data contain tunnel parameters of the packets. Furthermore, the at least one serial core unit receives the meta data from the parallel core units through several second data flows.

Abstract: A system including computer readable storage media including executable instructions and one or more processors configured to execute the executable instructions to obtain a schematic netlist and a performance specification for an integrated circuit, determine electrical constraints for nets in the schematic netlist based on the performance specification, determine physical constraints from the electrical constraints, rout the nets in the schematic netlist based on the electrical constraints and the physical constraints, and provide a data file of a layout.

Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.

Abstract: The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.

Abstract: A method includes moving a wafer transport device on a transport rail, wherein the wafer transport device comprises a hoist unit configured to grip a wafer container unit; stopping the wafer transport device above a load port; after stopping the wafer transport device, reading data of a rail mark located on the transport rail; aligning an orientation of the wafer transport device according to the data of the rail mark; after aligning the orientation of the wafer transport device according to the data of the rail mark, aligning the wafer transport device with respect to a top surface of the load port; after aligning the wafer transport device with respect to the top surface of the load port, lowering the hoist unit.

Abstract: A wafer stacking method includes the following steps. A first wafer is provided. A second wafer is bonded to the first wafer to form a first wafer stack structure. A first edge defect inspection is performed on the first wafer stack structure to find a first edge defect and measure a first distance in a radial direction between an edge of the first wafer stack structure and an end of the first edge defect away from the edge of the first wafer stack structure. A first trimming process with a range of a first width is performed from the edge of the first wafer stack structure to remove the first edge defect. Herein, the first width is greater than or equal to the first distance.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a plurality of gate structures arranged along a first side of a substrate within a plurality of pixel regions. An etch block structure is arranged on the first side of the substrate between neighboring ones of the plurality of gate structures. A contact etch stop layer (CESL) is arranged on the etch block structure between the neighboring ones of the plurality of gate structures. An isolation structure is disposed between one or more sidewalls of the substrate and extends from a second side of the substrate to the first side of the substrate. The etch block structure is vertically between the isolation structure and the CESL.

Abstract: Systems and methods are disclosed for determining a visual indicator for a package based on a delivery address for the package and a location of the delivery address along a delivery route. An optimized delivery route may be created for packages to be delivered at a given time. At the fulfillment center, a delivery system may label a package prior to loading the package on a delivery vehicle. The delivery system may determine the appropriate visual indicator (e.g., color and/or pattern) or the visual indicator may be randomly selected. The delivery system may generate a label having the visual indicator. The package may be deposited into a certain bin with other packages having a delivery address in close proximity. The delivery system may generate a user interface on a user device that indicates that the package has a certain visual indicator to facilitate sorting and identification of the package.

Abstract: A holographic calling system can capture and encode holographic data at a sender-side of a holographic calling pipeline and decode and present the holographic data as a 3D representation of a sender at a receiver-side of the holographic calling pipeline. The holographic calling pipeline can include stages to capture audio, color images, and depth images; densify the depth images to have a depth value for each pixel while generating parts masks and a body model; use the masks to segment the images into parts needed for hologram generation; convert depth images into a 3D mesh; paint the 3D mesh with color data; perform torso disocclusion; perform face reconstruction; and perform audio synchronization. In various implementations, different of these stages can be performed sender-side or receiver side. The holographic calling pipeline also includes sender-side compression, transmission over a communication channel, and receiver-side decompression and hologram output.

Abstract: A display apparatus includes a wireless transmission unit and a display panel. The display panel includes a substrate, a plurality of pixel units and a signal line. The substrate includes a display region and a periphery region. The periphery region surrounds the display region. The pixel units are disposed on the display region. Each of the pixel units includes an active device and a pixel electrode. The active device is electrically connected to the pixel electrode. The signal line is on the periphery region. As viewed from a top view, the signal line has an annular shape having a gap and surrounds the display region.

Abstract: An electronic device and a temperature detection device thereof are provided. The temperature detection device includes a differential stage circuit and an output stage circuit. The differential stage circuit includes a first differential end and a second differential end, and includes a cross-coupled transistor element, a first resistor and a second transistor. The cross-coupled transistor element receives a first voltage. The first resistor is coupled between the first differential end and a second voltage, and the first resistor is poly-silicon resistor. The second resistor is coupled between the second differential end and the second voltage, and the second resistor is a silicon carbide diffusion resistor. The output stage circuit generates a driving voltage according to a first control voltage on the first differential end and a second control voltage on the second differential end.

Abstract: A bonding structure for connecting a chip and a metal material, and a manufacturing method thereof are provided. The bonding structure includes a substrate, a chip, a metal member, at least one metal wire and an alloy connection layer. An upper surface of the substrate has a first metal pad and a second metal pad. The chip is disposed on the first metal pad. The metal member is disposed above the chip. The at least one metal wire has a first end and a second end, the first end is connected to an upper surface of the metal piece, and the second end is connected to the second metal pad. The alloy connection layer is connected between the metal member and the chip, and covers at least a part of a lower surface of the metal member.

Abstract: A system including computer readable storage media including executable instructions and one or more processors configured to execute the executable instructions to obtain a schematic netlist and a performance specification for an integrated circuit, determine electrical constraints for nets in the schematic netlist based on the performance specification, determine physical constraints from the electrical constraints, rout the nets in the schematic netlist based on the electrical constraints and the physical constraints, and provide a data file of a layout.

Abstract: The invention provides an optical coherence tomography self-testing system, an optical coherence tomography method and an ocular disease monitoring system. The optical coherence tomography self-testing system comprises a camera device, an external display module and a communication module. The camera device includes an image-capturing module and a processing module. The image-capturing module captures a plurality of ocular images. The processing module is connected to the image-capturing module, and the processing module determines whether a position offset value between the pupil center position of a tested eyeball and an optical axis of the image-capturing module is within a preset error range. If the position offset value is within the preset error range, the plurality of ocular images is stored as a plurality of displayed images. The external display module displays one of the plurality of displayed images and a status light after the image-capturing module has completed image capturing.

Abstract: A buffer assembly includes a screw rod, a base, a rotating element and a clamping ring. The rotating element is rotatably disposed on the base along a rotation axis. The rotating element includes a through hole. The clamping ring is detachably connected to the rotating element along a connection axis, so that the clamping ring is adapted to switch to a connected state or an open state. The clamping ring includes a position-limiting space, and the rotation axis is perpendicular to the connection axis. When the clamping ring is in the connected state, the position-limiting space and the through hole are located on the rotation axis, and the screw rod pushes the clamping ring to rotate so that the screw rod passes through the position-limiting space and the through hole. When the clamping ring is in the open state, the position-limiting space is misaligned with the rotation axis.

Abstract: A short-circuit protection circuitry is adapted for a power transistor. The short-circuit protection circuitry includes a first diode, a first resistor, a voltage dividing circuit, a gate voltage generator, a pull-down circuit, and a control signal generator. The first diode is coupled to a drain of the power transistor. The first resistor is coupled between the first diode and the power transistor. The voltage dividing circuit is coupled between a gate and a source of the power transistor to generate a dividing voltage. The gate voltage generator provides a gate voltage to the gate of the power transistor according to a first driving signal and a second driving signal. The pull-down circuit pulls down the gate voltage according to a control signal. The control signal generator generates the control signal according to the first driving signal, a voltage on the anode of the first diode and the dividing voltage.

Abstract: A method includes moving a wafer transport device to a position above a load port; lowering a hoist unit of the wafer transport device above the load port, wherein the wafer transport device has a plurality of belts, each of the belts is connected to the hoist unit and wound around a respective belt winding drum; detecting sound waves from the belts by using at least one acoustic sensor to measure tensions of the belts; and comparing the tensions from the belts to determine an inclination of the hoist unit.