Patents by Inventor Wei-Chi Chen
Wei-Chi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250138144Abstract: A time division duplexed (TDD) frequency modulation continuous wave (FMCW) radar system includes P transmitter circuit chains and M receiver circuit chains. The P transmitter circuit chains are used to transmit a plurality of FMCW signals. A pth transmitter circuit chain is coupled to a single pole Op throw (SPQPT) radio frequency (RF) switch, the SPOT RF switch is coupled to Op antennas, Qp and P are positive integers, and p is a positive integer not larger than P. The M receiver circuit chains are used to receive a plurality of reflected FMCW signals. An mth receiver circuit chain is coupled to a single pole Nm throw (SPNmT) radio frequency (RF) switch, the SPNmT RF switch is coupled to Nm antennas, Nm and M are positive integers, and m is a positive integer not larger than M.Type: ApplicationFiled: September 26, 2024Publication date: May 1, 2025Applicant: KaiKuTek INC.Inventors: Mike Chun-Hung Wang, Yi-Chu Chen, Tun-Yen Liao, Zi-Hao Fu, Hsiang-Chieh Jhan, Yi-Ting Tseng, Chun-Hsuan Kuo, Wei-Chi Li, Sheng-Tse Tai, Wei-Ming Sun, Pei-Ming Cai
-
Publication number: 20250140642Abstract: A thermoelectric cooler (TEC) is positioned to move heat away from a hot spot on a semiconductor chip and toward a dielectric substrate. This approach to thermal management is particularly effective when used in conjunction with a buried rail and back side power delivery. The TEC may be in a layer that contains solder connections be between two device layers an IC package. Alternatively, the TEC may be in a metal interconnect structure over the semiconductor substrate such as in a passivation stack at the top of the metal interconnect structure. TECs at either of these locations may be formed by wafer-level processing.Type: ApplicationFiled: March 6, 2024Publication date: May 1, 2025Inventors: Cheng-Ming Lin, Che Chi Shih, Wei-Yen Woon, Szuya Liao, Isha Datye, Sam Vaziri, Po-Yu Chen, Cheng Hung Wu, Wei-Pin Changchien, Xinyu Bao
-
Publication number: 20250139853Abstract: Disclosed are a method for generating a dot pattern and a computer-readable medium. The method for generating a dot pattern is applicable to a computer device which executes the method. The method for generating a dot pattern includes: generating a grayscale value weight based on a reference image; inputting a plurality of conversion parameters including a size range of dots, a total number of the dots, and a number of times of iterative operation; generating a plurality of initial random coordinates corresponding to the plurality of dots through a random operation based on the grayscale value weight, the size range of the dots, and the total number of the dots; and performing dot distribution processing on the dots based on the number of times of iterative operation, the grayscale value weight, and the initial random coordinates to generate a dot pattern, where the dot pattern includes the dots.Type: ApplicationFiled: April 9, 2024Publication date: May 1, 2025Inventors: SHIAN-CHI SU, SHIH-KUO CHEN, WEI-CHIEH LEE
-
Publication number: 20250129242Abstract: A resin composition is provided. The resin composition comprises: (A) a compound having a structure of formula (I); and (B) a component having ethylenically unsaturated double bond(s), which is selected from the group consisting of a compound having a structure of formula (II), a compound having a structure of formula (III), and combinations thereof, wherein Z, A, R, X, Y, m, and n are as defined in the specification.Type: ApplicationFiled: January 31, 2024Publication date: April 24, 2025Applicant: TAIWAN UNION TECHNOLOGY CORPORATIONInventors: JEN-CHI CHIANG, MENG-HUEI CHEN, WEI-HSIN HUANG
-
Patent number: 12283545Abstract: A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer.Type: GrantFiled: August 1, 2023Date of Patent: April 22, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chi Chu, Hung-Jui Kuo, Yu-Hsiang Hu, Wei-Chih Chen
-
Patent number: 12283637Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.Type: GrantFiled: October 31, 2022Date of Patent: April 22, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jian-Li Lin, Wei-Da Lin, Cheng-Guo Chen, Ta-Kang Lo, Yi-Chuan Chen, Huan-Chi Ma, Chien-Wen Yu, Kuan-Ting Lu, Kuo-Yu Liao
-
Publication number: 20250123429Abstract: An electronic device is provided. The electronic device includes a panel, a protective substrate, and a first light-shielding structure. The panel has an active area and a peripheral area. The peripheral area is adjacent to the active area. The protective substrate is disposed opposite to the panel. The first light-shielding structure is disposed on a surface of the protective substrate and corresponds to the peripheral area. A portion of the first light-shielding structure that overlaps the peripheral area has at least one opening.Type: ApplicationFiled: September 9, 2024Publication date: April 17, 2025Inventors: Yen-Chi CHANG, Min-Chien SUNG, Po-Tsun KUO, Yu-Kai WANG, Wei-Lun HSIAO, Cheng-Yang TSAI, Yu-Ting CHEN
-
Patent number: 12273035Abstract: A conversion control circuit controls plural stackable sub-converters which are coupled in parallel to generate an output power to a load, the conversion control circuit includes: a current sharing terminal, wherein a current sharing signal is configured to be connected to the current sharing terminals, in parallel, of the plurality of the conversion control circuits; and a current sharing circuit, configured to generate or receive the current sharing signal which is generated according to an output current of the output power; wherein the conversion control circuit adjusts the power stage circuit according to the current sharing signal for current sharing among the plural stackable sub-converters.Type: GrantFiled: March 21, 2023Date of Patent: April 8, 2025Assignee: Richtek Technology CorporationInventors: Ta-Yung Yang, Wei-Hsu Chang, Kuo-Chi Liu, Chao-Chi Chen
-
Publication number: 20250102621Abstract: In a radar sensor, a transmitting antenna is configured to radiate a transmitted RF signal, a receiving antenna is configured to receive a reflected RF signal from a target, and a frontend circuit is configured to calculate the distance between the target and the radar sensor by measuring the frequency shift between the transmitted RF signal and the reflected RF signal. The frontend circuit includes a crystal-less signal synthesizer configured to generate the transmitted RF signal without using a crystal, and a mixer configured to provide an IF-band signal associated with the frequency shift between the transmitted RF signal and the reflected RF signal by mixing the reflected RF signal and the transmitted RF signal.Type: ApplicationFiled: April 8, 2024Publication date: March 27, 2025Applicant: KaiKuTek INC.Inventors: Mike Chun-Hung Wang, Yi-Chu Chen, Tun-Yen Liao, Yi-Ting Tseng, Wei-Chi Li
-
Publication number: 20250096000Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first wafer is provided. The first wafer includes a first substrate and a first device layer. A second wafer is provided. The second wafer includes a second substrate and a second device layer. The second device layer is bonded to the first device layer. An edge trimming process is performed on the first wafer and the second wafer to expose a first upper surface of the first substrate and a second upper surface of the first substrate and to form a damaged region in the first substrate below the first upper surface and the second upper surface. The second upper surface is higher than the first upper surface. A first photoresist layer is formed. The first photoresist layer is located on the second wafer and the second upper surface and exposes the first upper surface and the damaged region. The damaged region is removed by using the first photoresist layer as a mask. The first photoresist layer is removed.Type: ApplicationFiled: October 16, 2023Publication date: March 20, 2025Applicant: United Microelectronics Corp.Inventors: Kun-Ju Li, Hsin-Jung Liu, Jhih Yuan Chen, I-Ming Lai, Ang Chan, Wei Xin Gao, Hsiang Chi Chien, Hao-Che Hsu, Chau Chung Hou, Zong Sian Wu
-
Patent number: 12255219Abstract: Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.Type: GrantFiled: July 20, 2023Date of Patent: March 18, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Chi Hung, Dun-Nian Yaung, Jen-Cheng Liu, Wei Chuang Wu, Yen-Yu Chen, Chih-Kuan Yu
-
Publication number: 20250081904Abstract: The present invention generally relates to a hydroponic culture medium and a hydroponic planting system, more particularly to a Houttuynia cordata hydroponic culture medium, a Houttuynia cordata hydroponic planting system, Houttuynia cordata extracts, a method, and applications thereof. The Houttuynia cordata hydroponic culture medium includes a plant fertilizer and a Houttuynia cordata growth-promoting additive. The Houttuynia cordata growth-promoting additive is selected from the group consisting of: vitamin B complex, seaweed essence, amino acid, microorganism, and a combination thereof. An electronic conductivity of the Houttuynia cordata hydroponic culture medium is between 0.4 ms/cm and 2.0 ms/cm.Type: ApplicationFiled: November 22, 2024Publication date: March 13, 2025Inventors: FANG-RONG CHANG, WEI-HUNG WU, YI-HONG TSAI, CHUNG-HSIEN CHEN, YEN-CHI LOO, HSUEH-ER CHEN, YEN-CHANG CHEN, HUI-PING HSIEH, CHEN HSIEH
-
Publication number: 20250080705Abstract: A projection device includes a light source module, a display panel, a freeform-surface reflective mirror, and a projection lens. The light source module includes a light source, a first Fresnel lens element, and a second Fresnel lens element. The first Fresnel lens element and the second Fresnel lens element are parallel to each other and located between the light source and the display panel. The display panel is arranged between the light source module and the freeform-surface reflective mirror. The projection lens is configured to transmit an image beam out of the projection device, and a direction of an optical axis of the projection lens is different from a direction of a normal of the first Fresnel lens element.Type: ApplicationFiled: August 22, 2024Publication date: March 6, 2025Applicant: Coretronic CorporationInventors: Kun-Zheng Lin, Wen-Chun Wang, Wei-Ting Wu, Wen-Chieh Chung, Jui-Chi Chen
-
Publication number: 20250068149Abstract: A data processing method applied in a data center is provided.Type: ApplicationFiled: December 20, 2023Publication date: February 27, 2025Applicants: Inventec (Pudong) Technology Corp., Inventec CorporationInventors: Wei-Chao Chen, Ming-Chi Chang, Ghih-Pin Wei, Jing-Lun Huang, Siang-Yu Lan, Shu-Huei Yang
-
Publication number: 20250068614Abstract: A data processing system is for uploading an upload data, wherein the upload data comprises a data content and a table name. The data processing system comprises a relational database; a NoSQL database; a data processing unit, coupled to the relational database and the NoSQL database, configured to execute a program code; and a storage unit, coupled to the data processing unit, configured to store the program code to instruct the data processing unit to execute a data processing method. The data processing method comprises determining a structure type of the upload data according to the data content; determining a first table of a first database according to the structure type, the data content and the table name of the upload data; and storing the upload data in the first table of the first database; wherein the first database is the relational database or the NoSQL database.Type: ApplicationFiled: December 19, 2023Publication date: February 27, 2025Applicants: Inventec (Pudong) Technology Corp., Inventec CorporationInventors: Wei-Chao Chen, Ming-Chi Chang, Chuo-Jui Wu, Jing-Lun Huang
-
Publication number: 20250063834Abstract: A polysilicon well is formed at a cross-road portion between a plurality of pixel sensors in a pixel sensor array. Moreover, the underlying oxide layer between the polysilicon well and a semiconductor layer of the pixel sensor array may be thinner than other areas of the oxide layer. The polysilicon well and the thinner oxide layer may reduce the likelihood of and/or the magnitude of lateral etching that occurs during etching of the semiconductor layer to form recesses in which a BDTI structure of the pixel sensor array is formed. Moreover, the bottom of the BDTI structure being surrounded by the polysilicon well enables a voltage bias to be applied to the BDTI structure through the polysilicon well to passivate damage that might have occurred to the semiconductor layer around the bottom of the BDTI structure.Type: ApplicationFiled: August 17, 2023Publication date: February 20, 2025Inventors: Chieh-En CHEN, Chen-Hsien LIN, Shyh-Fann TING, Wei-Chih WENG, Feng-Chi HUNG
-
Patent number: 12231436Abstract: A method for permission management includes: generating a plurality of job roles with different permissions according to organization permission table; generating first permission structure directed graph according to the job roles; selecting one of the job roles in first permission structure directed graph as target job role; generating minimum directed spanning graph in first permission structure directed graph according to target job role; determining whether permission of each of the job roles in first permission structure directed graph matches job of each of the job roles in first permission structure directed graph; and adjusting permission and job of each of the job roles to generate second permission structure directed graph if it is determined that permission of each of the job roles in first permission structure directed graph does not match job of each of the job roles in first permission structure directed graph.Type: GrantFiled: December 21, 2022Date of Patent: February 18, 2025Assignees: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATIONInventors: Wei-Chao Chen, Ming-Chi Chang, Chih-Pin Wei, Chuo-Jui Wu
-
Patent number: 12212736Abstract: A device for decoding video data includes a memory configured to store video data; and one or more processors implemented in circuitry and configured to: determine a deterministic bounding box from which to retrieve reference samples of reference pictures of video data for performing decoder-side motion vector derivation (DMVD) for a current block of the video data; derive a motion vector for the current block according to DMVD using the reference samples within the deterministic bounding box; form a prediction block using the motion vector; and decode the current block using the prediction block.Type: GrantFiled: June 27, 2022Date of Patent: January 28, 2025Assignee: QUALCOMM INCORPORATEDInventors: Chun-Chi Chen, Han Huang, Cheng-Teh Hsieh, Wei-Jung Chien, Zhi Zhang, Yao-Jen Chang, Yan Zhang, Vadim Seregin, Marta Karczewicz
-
Patent number: 12124989Abstract: Systems and methods are disclosed for determining a visual indicator for a package based on a delivery address for the package and a location of the delivery address along a delivery route. An optimized delivery route may be created for packages to be delivered at a given time. At the fulfillment center, a delivery system may label a package prior to loading the package on a delivery vehicle. The delivery system may determine the appropriate visual indicator (e.g., color and/or pattern) or the visual indicator may be randomly selected. The delivery system may generate a label having the visual indicator. The package may be deposited into a certain bin with other packages having a delivery address in close proximity. The delivery system may generate a user interface on a user device that indicates that the package has a certain visual indicator to facilitate sorting and identification of the package.Type: GrantFiled: July 14, 2022Date of Patent: October 22, 2024Assignee: Amazon Technologies, Inc.Inventors: Taimoor Jawaid Khizri, Matthew Kenneth Bellamy, Liron David Yedidsion, Shubham Dabas, Vipin Kumar Singla, Fnu Shashank Kumar, Devinder Singh, Shailendra Singh Rajawat, William Wei-Chi Chen, Arnav Anshul
-
Patent number: 11128066Abstract: A conductive component structure of conductive wire connection device is more securely assembled with the conductive wire to enhance the electro-conduction performance. The conductive component includes a main body in the form of a plate body and a restriction body connected on the main body. The restriction body has a base section, a first arm and a second arm connected with the base section and free sections connected with the first and second arms, which together provide elastic holding action force for the restriction body. When the conductive wire is plugged into the case into contact with the conductive component, the rear end of the conductive wire is at least securely pressed between the first and second arms of the restriction body without deflecting or swinging due to external force.Type: GrantFiled: March 13, 2019Date of Patent: September 21, 2021Assignees: Switchlab Inc., Switchlab (Shanghai) Co., Ltd., Gaocheng Electronics Co., Ltd.Inventors: Chih-Yuan Wu, Wei-Chi Chen, Ming-Shan Tai