Abstract: A package structure includes a first semiconductor die, a second semiconductor die, an insulating encapsulant and a redistribution layer. The insulating encapsulant laterally surrounds the first semiconductor die and the second semiconductor die, wherein the insulating encapsulant includes a first portion sandwiched in between the first semiconductor die and the second semiconductor die, the first portion has a first recessed part adjacent to an edge of the first semiconductor die, and a second recessed part adjacent to an edge of the second semiconductor die. The redistribution layer is disposed on and electrically connected to the first semiconductor die and the second semiconductor die.

Abstract: A projection device includes a light source module, a display panel, a freeform-surface reflective mirror, and a projection lens. The light source module includes a light source, a first Fresnel lens element, and a second Fresnel lens element. The first Fresnel lens element and the second Fresnel lens element are parallel to each other and located between the light source and the display panel. The display panel is arranged between the light source module and the freeform-surface reflective mirror. The projection lens is configured to transmit an image beam out of the projection device, and a direction of an optical axis of the projection lens is different from a direction of a normal of the first Fresnel lens element.

Abstract: A polysilicon well is formed at a cross-road portion between a plurality of pixel sensors in a pixel sensor array. Moreover, the underlying oxide layer between the polysilicon well and a semiconductor layer of the pixel sensor array may be thinner than other areas of the oxide layer. The polysilicon well and the thinner oxide layer may reduce the likelihood of and/or the magnitude of lateral etching that occurs during etching of the semiconductor layer to form recesses in which a BDTI structure of the pixel sensor array is formed. Moreover, the bottom of the BDTI structure being surrounded by the polysilicon well enables a voltage bias to be applied to the BDTI structure through the polysilicon well to passivate damage that might have occurred to the semiconductor layer around the bottom of the BDTI structure.

Abstract: Method to implement heat dissipation multilayer and reduce thermal boundary resistance for high power consumption semiconductor devices is provided. The heat dissipation multilayer comprises a first crystalline layer that possesses a first phonon frequency range, a second crystalline layer that has a second phonon frequency range which does not overlap with the first phonon frequency range, and an amorphous layer located between the first and second crystalline layers. The amorphous layer has a third phonon frequency range that overlaps both the first and second phonon frequency ranges.

Abstract: A memory device is provided which includes a first memory cell including a first transistor and a second transistor coupled to the first transistor in parallel. Gates of the first transistor and the second transistor are coupled to each other, and the gates of the first transistor and the second transistor pass different layers and overlap with each other. Types of the first transistor and the second transistor are the same.

Abstract: Provided is a lentivirus packaging system, which comprises: a transfer plasmid comprising a nucleotide sequence of TAR-reserved-chimeric 5? long terminal repeat (LTR); at least one packaging plasmid comprising a nucleotide sequence encoding TAR RNA binding protein, a nucleotide sequence of rev gene, a nucleotide sequence of gag gene, and a nucleotide sequence of pol gene; and an envelope plasmid. Due to the expression of gene of TAR RNA binding protein by the packaging plasmids, the produced lentivirus has higher virus titer and can improve the transduction rate and the gene delivery efficiency during cell transduction. The present invention further provides a method of improving lentivirus production in a host cell, which comprises using the lentivirus packaging system to transfect the host cell. The present invention further provides a cell transduced by the lentivirus and a method of using the cell for treating cancer.

Abstract: The present disclosure is related to a lead frame structure. The lead frame structure includes a bottom board and a blocking wall. The bottom board has a first conductive portion and a second conductive portion. The first conductive portion separates from the second conductive portion. The first and second conductive portions are configured to electrically connect to a light source. The blocking wall is located on the bottom board, and the blocking wall surrounds an opening. The first and the second conductive portions are exposed from the opening. The first and the second conductive portions each have an extending portion. The extending portion extends beyond an external surface of the blocking wall in a horizontal direction.

Abstract: Provided is a lentivirus packaging system, which comprises: a transfer plasmid comprising a nucleotide sequence of TAR-reserved-chimeric 5? long terminal repeat (LTR); at least one packaging plasmid comprising a nucleotide sequence encoding TAR RNA binding protein, a nucleotide sequence of rev gene, a nucleotide sequence of gag gene, and a nucleotide sequence of pol gene; and an envelope plasmid. Due to the expression of gene of TAR RNA binding protein by the packaging plasmids, the produced lentivirus has higher virus titer and can improve the transduction rate and the gene delivery efficiency during cell transduction. The present invention further provides a method of improving lentivirus production in a host cell, which comprises using the lentivirus packaging system to transfect the host cell. The present invention further provides a cell transduced by the lentivirus and a method of using the cell for treating cancer.

Abstract: A direct-type light source module including N-stage light sources and an optical sheet is provided. The optical sheet is disposed above the N-stage light sources, and an optical distance between the i-th-stage light source and the optical sheet is smaller than an optical distance between the i+1-th-stage light source and the optical sheet, where 1?i<N, and N is a positive integer greater than 1. A display device is also provided.

Abstract: The present disclosure is related to a lead frame structure. The lead frame structure includes a bottom board and a blocking wall. The bottom board has a first conductive portion and a second conductive portion. The first conductive portion separates from the second conductive portion. The first and second conductive portions are configured to electrically connect to a light source. The blocking wall is located on the bottom board, and the blocking wall surrounds an opening. The first and the second conductive portions are exposed from the opening. The first and the second conductive portions each have an extending portion. The extending portion extends beyond an external surface of the blocking wall in a horizontal direction.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a substrate, the substrate includes a first fin, a second fin, and an isolation region disposed between the first fin and the second fin. The second fin includes a different material than a material of the substrate. The method includes forming an oxide over the first fin, the second fin, and a top surface of the isolation region at a temperature of about 400 degrees C. or less, and post-treating the oxide at a temperature of about 600 degrees C. or less.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a substrate, the substrate includes a first fin, a second fin, and an isolation region disposed between the first fin and the second fin. The second fin includes a different material than a material of the substrate. The method includes forming an oxide over the first fin, the second fin, and a top surface of the isolation region at a temperature of about 400 degrees C. or less, and post-treating the oxide at a temperature of about 600 degrees C. or less.

Abstract: A touch panel is provided. The touch panel having a pixel area and a sensing area includes a first substrate and an opposite second substrate. A press sensing spacer is disposed on the sensing area of the first substrate. A press sensing stage is disposed on the sensing area of the second substrate, corresponding to the press sensing spacer. An alignment layer is disposed over the second substrate, covering the press sensing stage and the pixel area of the second substrate. In an embodiment, the height of the press sensing stage is greater than the height from the surface of the second substrate at the pixel area to the bottom of the alignment layer by at least 0.05 ?m.

Abstract: A method and a control board for eliminating power-off residual images in a display and a display using the same are provided. The method includes the following steps of providing a first voltage to compensate a second voltage which is used for sequentially turning on all scan lines within a display panel when the display is in power-off, and then forming a third voltage to turn on all scan lines within the display panel according to the compensated second voltage.

Abstract: A touch panel is provided. The touch panel having a pixel area and a sensing area includes a first substrate and an opposite second substrate. A press sensing spacer is disposed on the sensing area of the first substrate. A press sensing stage is disposed on the sensing area of the second substrate, corresponding to the press sensing spacer. An alignment layer is disposed over the second substrate, covering the press sensing stage and the pixel area of the second substrate. In an embodiment, the height of the press sensing stage is greater than the height from the surface of the second substrate at the pixel area to the bottom of the alignment layer by at least 0.05 ?m.

Abstract: A backlight module includes a back plate structure, a light source disposed in the back plate structure, at least one wire connected to the light source, and at least one wire fixing frame fixed on the back plate structure. Each wire fixing frame includes a main part, a first fixing part disposed on a side of the main part, a second fixing part disposed on a side of the main part and opposite to the first fixing part, and an extending part extending in a direction from the second fixing part to the first fixing part. A wire outlet is defined between the extending part and the first fixed part, and a wire inlet is opposite to the wire outlet. A wire hold space is defined among the main part, the first fixing part, the second fixing part, and the back plate structure.

Abstract: A backlight module includes a back plate structure, a light source disposed in the back plate structure, at least one wire connected to the light source, and at least one wire fixing frame fixed on the back plate structure. Each wire fixing frame includes a main part, a first fixing part disposed on a side of the main part, a second fixing part disposed on a side of the main part and opposite to the first fixing part, and an extending part extending in a direction from the second fixing part to the first fixing part. A wire outlet is defined between the extending part and the first fixed part, and a wire inlet is opposite to the wire outlet. A wire hold space is defined among the main part, the first fixing part, the second fixing part, and the back plate structure.

Abstract: A wire fixing frame for fixing at least one wire on a substrate is described. The wire fixing frame includes a main part, a first fixing part, a second fixing part, and an extending part. A wire outlet is defined between the extending part and the first fixed part, and a wire inlet is opposite to the wire outlet. A wire hold space is defined among the main part, the first fixing part, the second fixing part, and the substrate. The wire passes from the wire inlet to the wire outlet through the wire hold space, and the wire is fixed at a position by a round corner of the first fixing part and the extending part.

Abstract: A method and a control board for eliminating power-off residual images in a display and a display using the same are provided. The method includes the following steps of providing a first voltage to compensate a second voltage which is used for sequentially turning on all scan lines within a display panel when the display is in power-off, and then forming a third voltage to turn on all scan lines within the display panel according to the compensated second voltage.

Abstract: A liquid crystal display module with backlight module providing an enhancement coefficient of the brightness enhancement film (BEF) within the range of 0.1 to 0.5. The backlight module is disposed behind the display panel and comprises a bottom diffuser, a brightness enhancement film, and a top diffuser disposed on the brightness enhancement film. A set of polarizers is disposed above and below the liquid crystal display panel. The backlight module meets TCO standards and has improved optical performance.