Patents by Inventor Wei-Chia Chen

Wei-Chia Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10494334
    Abstract: Provided are novel benzenesulfonamide compounds that inhibit calcium/calmodulin-dependent protein kinase II (CaMKII) and pharmaceutical compositions containing the benzenesulfonamide compounds. Also provided are methods of using the benzenesulfonamide compounds to treat diseases or conditions that are associated with CaMKII activity, such as a flavivirus infection.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: December 3, 2019
    Assignee: ACADEMIA SINICA
    Inventors: Wen-Shan Li, Yi-Ling Lin, Wei-Chia Chen, Yogy Simanjuntak
  • Publication number: 20190300475
    Abstract: Provided are novel benzenesulfonamide compounds that inhibit calcium/calmodulin-dependent protein kinase II (CaMKII) and pharmaceutical compositions containing the benzenesulfonamide compounds. Also provided are methods of using the benzenesulfonamide compounds to treat diseases or conditions that are associated with CaMKII activity, such as a flavivirus infection.
    Type: Application
    Filed: March 20, 2019
    Publication date: October 3, 2019
    Inventors: Wen-Shan Li, Yi-Ling Lin, Wei-Chia Chen, Yogy Simanjuntak
  • Patent number: 8395139
    Abstract: A memory structure includes an active area surrounded by first isolation trenches and second isolation trenches; a bit line trench recessed into the active area of the semiconductor substrate; a word line trench recessed into the active area of the semiconductor substrate and being shallower than the bit line trench. The bit line trench and the word line trench together divide the active area into four pillar-shaped sub-regions. A bit line is embedded in the bit line trench. A word line is embedded in the word line trench. A vertical transistor is built in each of the pillar-shaped sub-regions. A resistive memory element is electrically coupled to the vertical transistor.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: March 12, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Hsin-Jung Ho, Chang-Rong Wu, Wei-Chia Chen