Patents by Inventor Wei-Chia Chen

Wei-Chia Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11976776
    Abstract: A stand adjustment device has a tripod-connecting member, a connecting seat, a proximal clamping plate, a boom-connecting tube, a locking shaft, and a manual operating member. The connecting seat is rotatably located around the tripod-connecting member. The proximal clamping plate is detachably attached to a side of the connecting seat. One end of the locking shaft is movably disposed in the boom-connecting tube. The boom is slidably mounted through the boom-connecting tube and the locking shaft. The locking shaft is slidably mounted through the boom-connecting tube, the proximal clamping plate, and the connecting seat such that the boom-connecting tube is rotatable relative to the connecting seat. The manual operating member and the locking shaft are configured to clamp the boom-connecting tube, the proximal clamping plate, and the connecting seat therebetween into a locked condition.
    Type: Grant
    Filed: May 30, 2023
    Date of Patent: May 7, 2024
    Assignee: RELIANCE INTERNATIONAL CORP.
    Inventors: Pei-Chi Chu, Cheng-Lin Ho, Chi-Chia Huang, Wei-Ting Chen
  • Patent number: 11956994
    Abstract: The present disclosure is generally related to 3D imaging capable OLED displays. A light field display comprises an array of 3D light field pixels, each of which comprises an array of corrugated OLED pixels, a metasurface layer disposed adjacent to the array of 3D light field pixels, and a plurality of median layers disposed between the metasurface layer and the corrugated OLED pixels. Each of the corrugated OLED pixels comprises primary or non-primary color subpixels, and produces a different view of an image through the median layers to the metasurface to form a 3D image. The corrugated OLED pixels combined with a cavity effect reduce a divergence of emitted light to enable effective beam direction manipulation by the metasurface. The metasurface having a higher refractive index and a smaller filling factor enables the deflection and direction of the emitted light from the corrugated OLED pixels to be well controlled.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: April 9, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Chung-Chih Wu, Hoang Yan Lin, Guo-Dong Su, Zih-Rou Cyue, Li-Yu Yu, Wei-Kai Lee, Guan-Yu Chen, Chung-Chia Chen, Wan-Yu Lin, Gang Yu, Byung-Sung Kwak, Robert Jan Visser, Chi-Jui Chang
  • Publication number: 20240096806
    Abstract: A method for manufacturing a semiconductor structure is provided. A substrate including a fin structure is received, provided or formed. A sacrificial gate layer is formed over the fin structure and a source/drain structure is formed adjacent to the sacrificial gate layer, wherein the sacrificial gate layer is surrounded by a dielectric structure. The sacrificial gate layer is removed, wherein a recess is defined by the dielectric structure. A work function layer is formed in the recess, wherein the work function layer includes an overhang portion at an opening of the recess. A thickness of the work function layer is reduced. A glue layer is formed over the work function layer. A semiconductor structure thereof is also provided.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 21, 2024
    Inventors: CHAO-HSUAN CHEN, WEI CHEN HUNG, LI-WEI YIN, YU-HSIEN LIN, YIH-ANN LIN, RYAN CHIA-JEN CHEN
  • Patent number: 11917422
    Abstract: An information handling system executing an intelligent throughput performance analysis and issue detection system may comprise a network interface device to establish a wireless link with a wireless network and a processor to execute a neural network trained to predict wireless link throughput values based on controlled connectivity testing metrics gathered in a controlled laboratory from tested information handling systems. The processor may gather measured throughput of the wireless link and operational connectivity metrics for the information handling system that describe antenna positional information, antenna adaptation controller parameters, signal strength measurements, and wireless link performance metrics. The neural network may output, based on the gathered operational connectivity metrics a predicted throughput value that differs from the measured throughput by a maximum tolerance.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: February 27, 2024
    Assignee: Dell Products, LP
    Inventors: Wei-Chia Huang, Chuang-Yueh Chen, YungShun Lin, Alan Eric Sicher, Lars Fredrik Proejts
  • Patent number: 10494334
    Abstract: Provided are novel benzenesulfonamide compounds that inhibit calcium/calmodulin-dependent protein kinase II (CaMKII) and pharmaceutical compositions containing the benzenesulfonamide compounds. Also provided are methods of using the benzenesulfonamide compounds to treat diseases or conditions that are associated with CaMKII activity, such as a flavivirus infection.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: December 3, 2019
    Assignee: ACADEMIA SINICA
    Inventors: Wen-Shan Li, Yi-Ling Lin, Wei-Chia Chen, Yogy Simanjuntak
  • Publication number: 20190300475
    Abstract: Provided are novel benzenesulfonamide compounds that inhibit calcium/calmodulin-dependent protein kinase II (CaMKII) and pharmaceutical compositions containing the benzenesulfonamide compounds. Also provided are methods of using the benzenesulfonamide compounds to treat diseases or conditions that are associated with CaMKII activity, such as a flavivirus infection.
    Type: Application
    Filed: March 20, 2019
    Publication date: October 3, 2019
    Inventors: Wen-Shan Li, Yi-Ling Lin, Wei-Chia Chen, Yogy Simanjuntak
  • Patent number: 8395139
    Abstract: A memory structure includes an active area surrounded by first isolation trenches and second isolation trenches; a bit line trench recessed into the active area of the semiconductor substrate; a word line trench recessed into the active area of the semiconductor substrate and being shallower than the bit line trench. The bit line trench and the word line trench together divide the active area into four pillar-shaped sub-regions. A bit line is embedded in the bit line trench. A word line is embedded in the word line trench. A vertical transistor is built in each of the pillar-shaped sub-regions. A resistive memory element is electrically coupled to the vertical transistor.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: March 12, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Hsin-Jung Ho, Chang-Rong Wu, Wei-Chia Chen