Patents by Inventor Wei-Chiang Shih
Wei-Chiang Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955507Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.Type: GrantFiled: September 9, 2021Date of Patent: April 9, 2024Assignee: AU OPTRONICS CORPORATIONInventors: Hsin-Hung Li, Wei-Syun Wang, Chih-Chiang Chen, Yu-Cheng Shih, Cheng-Chan Wang, Chia-Hsin Chung, Ming-Jui Wang, Sheng-Ming Huang
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Patent number: 10795767Abstract: An error correcting system is provided. The error correcting system includes an error correcting code (ECC) circuit and a control circuit. The ECC circuit is configured to encode input data received from M input terminals to generate encoded data in response to a write operation, and output the encoded data. The input data includes write data associated with the write operation, and the encoded data includes the input data and associated parity data. The control circuit is coupled to at least one of the M input terminals. When the write operation is directed to a memory device having a data bit width less than M bits, the write data is inputted to a portion of the M input terminals, the control circuit is configured to provide reference data to another portion of the M input terminals, and the write data and the reference data serve as the input data.Type: GrantFiled: December 26, 2018Date of Patent: October 6, 2020Assignee: M31 TECHNOLOGY CORPORATIONInventors: Zhi-Xian Chou, Wei-Chiang Shih
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Publication number: 20200210289Abstract: An error correcting system is provided. The error correcting system includes an error correcting code (ECC) circuit and a control circuit. The ECC circuit is configured to encode input data received from M input terminals to generate encoded data in response to a write operation, and output the encoded data. The input data includes write data associated with the write operation, and the encoded data includes the input data and associated parity data. The control circuit is coupled to at least one of the M input terminals. When the write operation is directed to a memory device having a data bit width less than M bits, the write data is inputted to a portion of the M input terminals, the control circuit is configured to provide reference data to another portion of the M input terminals, and the write data and the reference data serve as the input data.Type: ApplicationFiled: December 26, 2018Publication date: July 2, 2020Inventors: ZHI-XIAN CHOU, WEI-CHIANG SHIH
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Patent number: 10692568Abstract: A memory device includes: at least one memory cell; a bit line connected to the at least one memory cell; a write controller; a write driver receiving a logic signal from an output terminal of the write controller, and driving the bit line based on the logic signal; a negative voltage generator generating a reference voltage for receipt by a ground terminal of the write driver; and a protector connected to one of a power terminal and the output terminal of the write controller. The protector is capable of releasing stress voltage of the write driver.Type: GrantFiled: September 13, 2018Date of Patent: June 23, 2020Assignee: M31 TECHNOLOGY CORPORATIONInventors: Shyh-Chyi Yang, Wei-Chiang Shih
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Patent number: 10692567Abstract: A method for assisting a memory cell in an access operation is provided. The method includes: setting a supply voltage to a first supply voltage level to determine a reference probability value of the memory cell applied by the first supply voltage level; applying an assist voltage to an access line coupled to the memory cell, and setting the supply voltage to a second supply voltage level to determine a relationship between the assist voltage and the access failure probability of the memory cell applied by the second supply voltage level; determining, from the relationship, a target assist voltage level of the assist voltage corresponding to the reference probability value; and providing an assist circuit configured to apply the target assist voltage level to the access line during the access operation, wherein the memory cell is applied by the second supply voltage level during the access operation.Type: GrantFiled: September 6, 2018Date of Patent: June 23, 2020Assignee: M31 TECHNOLOGY CORPORATIONInventors: Zhi-Xian Chou, Wei-Chiang Shih
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Publication number: 20200082875Abstract: A method for assisting a memory cell in an access operation is provided. The method includes: setting a supply voltage to a first supply voltage level to determine a reference probability value of the memory cell applied by the first supply voltage level; applying an assist voltage to an access line coupled to the memory cell, and setting the supply voltage to a second supply voltage level to determine a relationship between the assist voltage and the access failure probability of the memory cell applied by the second supply voltage level; determining, from the relationship, a target assist voltage level of the assist voltage corresponding to the reference probability value; and providing an assist circuit configured to apply the target assist voltage level to the access line during the access operation, wherein the memory cell is applied by the second supply voltage level during the access operation.Type: ApplicationFiled: September 6, 2018Publication date: March 12, 2020Inventors: ZHI-XIAN CHOU, WEI-CHIANG SHIH
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Publication number: 20190088311Abstract: A memory device includes: at least one memory cell; a bit line connected to the at least one memory cell; a write controller; a write driver receiving a logic signal from an output terminal of the write controller, and driving the bit line based on the logic signal; a negative voltage generator generating a reference voltage for receipt by a ground terminal of the write driver; and a protector connected to one of a power terminal and the output terminal of the write controller. The protector is capable of releasing stress voltage of the write driver.Type: ApplicationFiled: September 13, 2018Publication date: March 21, 2019Inventors: Shyh-Chyi YANG, Wei-Chiang SHIH
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Patent number: 9378808Abstract: A pulse width modulation device for use in an N-ports random access memory having a plurality of word line sets, wherein a specified word line set comprises N port word lines. The pulse width modulation device comprises a status detecting device and a clock signal generator. The status detecting device is coupled to the N port word lines having a first and a second port word line, and outputs a first control signal when both the voltage values of the first and second port word lines are within a first level range. The clock signal generator is coupled to the status detecting device and the specified word line set, and generates and outputs a first clock signal to the specified word line set, wherein a duration of the first clock signal kept within the first level range is variable in response to the first control signal.Type: GrantFiled: January 23, 2015Date of Patent: June 28, 2016Assignee: M31 Technology CorporationInventors: Nan-Chun Lien, Chen-Wei Lin, Chao-Kuei Chung, Li-Wei Chu, Yuh-Jiun Lin, Yu-Wei Yeh, Wei-Chiang Shih
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Publication number: 20160111144Abstract: A pulse width modulation device for use in an N-ports random access memory having a plurality of word line sets, wherein a specified word line set comprises N port word lines. The pulse width modulation device comprises a status detecting device and a clock signal generator. The status detecting device is coupled to the N port word lines having a first and a second port word line, and outputs a first control signal when both the voltage values of the first and second port word lines are within a first level range. The clock signal generator is coupled to the status detecting device and the specified word line set, and generates and outputs a first clock signal to the specified word line set, wherein a duration of the first clock signal kept within the first level range is variable in response to the first control signal.Type: ApplicationFiled: January 23, 2015Publication date: April 21, 2016Inventors: Nan-Chun LIEN, Chen-Wei Lin, Chao-Kuei CHUNG, Li-Wei CHU, Yuh-Jiun LIN, Yu-Wei YEH, Wei-Chiang SHIH
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Patent number: 9213789Abstract: A method of generating optimized memory instances using a memory compiler is disclosed. Data pertinent to describing a memory to be designed are provided, and front-end models and back-end models are made to supply a library. Design criteria are received via a user interface. Design of the memory is optimized among speed, power and area according to the provided library and the received design criteria, thereby generating memory instances.Type: GrantFiled: December 13, 2012Date of Patent: December 15, 2015Assignee: M31 TECHNOLOGY CORPORATIONInventors: Nan-Chun Lien, Hsiao-Ping Lin, Wei-Chiang Shih, Yu-Chun Lin, Yu-Wei Yeh
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Patent number: 8804445Abstract: The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.Type: GrantFiled: May 31, 2012Date of Patent: August 12, 2014Assignee: National Chiao Tung UniversityInventors: Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee
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Publication number: 20140173241Abstract: A method of generating optimized memory instances using a memory compiler is disclosed. Data pertinent to describing a memory to be designed are provided, and front-end models and back-end models are made to supply a library. Design criteria are received via a user interface. Design of the memory is optimized among speed, power and area according to the provided library and the received design criteria, thereby generating memory instances.Type: ApplicationFiled: December 13, 2012Publication date: June 19, 2014Applicant: M31 TECHNOLOGY CORPORATIONInventors: Nan-Chun Lien, Hsiao-Ping Lin, Wei-Chiang Shih, Yu-Chun Lin, Yu-Wei Yeh
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Patent number: 8659936Abstract: A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices.Type: GrantFiled: December 28, 2010Date of Patent: February 25, 2014Assignees: Faraday Technology Corp., National Chiao Tung UniversityInventors: Ching-Te Chuang, Hao-I Yang, Mao-Chih Hsia, Wei Hwang, Chia-Cheng Chen, Wei-Chiang Shih
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Publication number: 20130301343Abstract: A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage selectors, a resistor, an amplifier and the SRAM are connected in a negative feedback way. Different bias voltages are applied to the SRAM for measuring threshold voltages of two FETs of the other inverter and the FET coupled to the other inverter. The present invention uses a single circuit to measure the threshold voltages of the three FETs without changing the physical structure of the SRAM. Thereby is accelerated the measurement and decreased the cost of the fabrication process and measurement instruments.Type: ApplicationFiled: August 29, 2012Publication date: November 14, 2013Inventors: Ching-Te Chuang, Shyh-Jye Jou, Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee, Jyun-Kai Chu
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Patent number: 8582378Abstract: A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage selectors, a resistor, an amplifier and the SRAM are connected in a negative feedback way. Different bias voltages are applied to the SRAM for measuring threshold voltages of two FETs of the other inverter and the FET coupled to the other inverter. The present invention uses a single circuit to measure the threshold voltages of the three FETs without changing the physical structure of the SRAM. Thereby is accelerated the measurement and decreased the cost of the fabrication process and measurement instruments.Type: GrantFiled: August 29, 2012Date of Patent: November 12, 2013Assignee: National Chiao Tung UniversityInventors: Ching-Te Chuang, Shyh-Jye Jou, Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee, Jyun-Kai Chu
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Publication number: 20130222071Abstract: The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.Type: ApplicationFiled: May 31, 2012Publication date: August 29, 2013Applicant: National Chiao Tung UniversityInventors: Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee
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Publication number: 20130223136Abstract: The present invention provides a 6T SRAM including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor. The first inverter zs a first pull-up transistor and a first pull-down transistor. The second inverter includes a second pull-up transistor and a second pull-down transistor. The gate of the second pull-up transistor is coupled with the gate of the second pull-down transistor, and the drain of the second pull-up transistor is coupled with the drain of the second pull-down transistor. The SRAM can measure the trip voltage, the read disturb voltage, and the write margin by controlling the first bit line, the second bit line, the GND, the first word line, and the voltage source without changing of the physic parameter of the SRAM.Type: ApplicationFiled: May 31, 2012Publication date: August 29, 2013Applicant: National Chiao Tung UniversityInventors: Ching-Te CHUANG, Shyh-Jye Jou, Wei Hwang, Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee
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Patent number: 8345504Abstract: A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.Type: GrantFiled: January 19, 2011Date of Patent: January 1, 2013Assignees: Faraday Technology Corp., National Chiao Tung UniversityInventors: Ching-Te Chuang, Hao-I Yang, Yi-Wei Lin, Wei Hwang, Wei-Chiang Shih, Chia-Cheng Chen
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Patent number: 8325512Abstract: SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal.Type: GrantFiled: March 24, 2011Date of Patent: December 4, 2012Assignee: Faraday Technology Corp.Inventors: Ching-Te Chuang, Wei-Chiang Shih, Hung-Yu Lee, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Kun-Di Lee
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Patent number: 8320164Abstract: A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.Type: GrantFiled: January 5, 2011Date of Patent: November 27, 2012Assignees: Faraday Technology Corp., National Chiao Tung UniversityInventors: Ching-Te Chuang, Hao-I Yang, Mao-Chih Hsia, Yung-Wei Lin, Chien-Yu Lu, Ming-Hsien Tu, Wei Hwang, Shyh-Jye Jou, Chia-Cheng Chen, Wei-Chiang Shih