Patents by Inventor Wei-Chieh FANG

Wei-Chieh FANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Buffer circuit and voltage generator using the same
    Patent number: 10033358
    Abstract: A buffer circuit includes a transistor cascode circuit, a latch circuit, a first transistor, a second transistor, and a voltage generator. The transistor cascode circuit is biasing at a first voltage. The latch circuit is biasing at a second voltage, whose voltage level is negative. The first transistor and the second transistor are coupling between the transistor cascode circuit and the latch circuit, and a gate of the first transistor is coupled to a gate of the second transistor. The voltage generator provides a biasing voltage to the gate of the first transistor and adjusts a voltage level of the biasing voltage dynamically according to a voltage level of the second voltage. The biasing voltage is at a first level when the buffer circuit is initially turned on, and the biasing voltage is at a second level when the buffer circuit enters the steady state.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: July 24, 2018
    Assignee: ALI CORPORATION
    Inventors: Wei-Chieh Fang, Chien-Yuan Lu
  • BUFFER CIRCUIT AND VOLTAGE GENERATOR USING THE SAME
    Publication number: 20170141767
    Abstract: A buffer circuit includes a transistor cascode circuit, a latch circuit, a first transistor, a second transistor, and a voltage generator. The transistor cascode circuit is biasing at a first voltage. The latch circuit is biasing at a second voltage, whose voltage level is negative. The first transistor and the second transistor are coupling between the transistor cascode circuit and the latch circuit, and a gate of the first transistor is coupled to a gate of the second transistor. The voltage generator provides a biasing voltage to the gate of the first transistor and adjusts a voltage level of the biasing voltage dynamically according to a voltage level of the second voltage. The biasing voltage is at a first level when the buffer circuit is initially turned on, and the biasing voltage is at a second level when the buffer circuit enters the steady state.
    Type: Application
    Filed: October 6, 2016
    Publication date: May 18, 2017
    Applicant: ALi Corporation
    Inventors: Wei-Chieh FANG, Chien-Yuan LU
  • Tablet computer
    Patent number: D1026916
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: May 14, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Hao-Jen Fang, Kung-Ju Chen, Wei-Yi Chang, Chun-Chieh Chen, Chih-Wen Chiang, Sheng-Hung Lee