Abstract: A BIOS backup/recovery system includes a chassis housing a BIOS backup/recovery subsystem coupled to a primary and a secondary BIOS storage system. The BIOS backup/recovery subsystem begins initialization operations and determines whether the primary BIOS storage system includes customized MAC addresses. If so, the BIOS backup/recovery subsystem determines whether MAC addresses in the secondary BIOS storage system match the customized MAC addresses in the primary BIOS storage system and, if not, performs a BIOS backup operation that includes copying the customized MAC addresses in the primary BIOS storage system to the secondary BIOS storage system. If not, the BIOS backup/recovery subsystem determines whether MAC addresses in the secondary BIOS storage system match default MAC addresses in the primary BIOS storage system and, if not, performs a BIOS recovery operation that includes copying customized MAC addresses in the secondary BIOS storage system to the primary BIOS storage system.

Abstract: A BIOS backup/recovery system includes a chassis housing a BIOS backup/recovery subsystem coupled to a primary and a secondary BIOS storage system. The BIOS backup/recovery subsystem begins initialization operations and determines whether the primary BIOS storage system includes customized MAC addresses. If so, the BIOS backup/recovery subsystem determines whether MAC addresses in the secondary BIOS storage system match the customized MAC addresses in the primary BIOS storage system and, if not, performs a BIOS backup operation that includes copying the customized MAC addresses in the primary BIOS storage system to the secondary BIOS storage system. If not, the BIOS backup/recovery subsystem determines whether MAC addresses in the secondary BIOS storage system match default MAC addresses in the primary BIOS storage system and, if not, performs a BIOS recovery operation that includes copying customized MAC addresses in the secondary BIOS storage system to the primary BIOS storage system.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a logic cell. The logic cell includes a first transistor and a second transistor. The first transistor includes a first gate structure extending in a first direction and overlapping a first semiconductor fin. The second transistor includes a second gate structure extending in the first direction and overlapping the first semiconductor fin and a second semiconductor fin. The first and second semiconductor fins extend in a second direction that is perpendicular to the first direction. The first and second transistors share a source/drain region, and one end of the first gate structure is formed between the first and second semiconductor fins.

Abstract: A base station (BS), a subordinated station (SS) and the transmission methods thereof for use in a multi-input multi-output (MIMO) network are provided. The BS stores resource allocation information about the MIMO network and an SS list, and generate a super frame according to the resource allocation information and the SS list. The super frame comprises a pilot pattern which comprises a plurality of pilots and data. The BS and SS both considers the pilot pattern as an identifier of the SS. When there are communications occurred between the BS and the SS, the BS/SS will confirm whether the pilot pattern of the super frame matches the identifier of the SS to reduce interference from other stations in the MIMO network.

Abstract: A base station (BS), a subordinated station (SS) and the transmission methods thereof for use in a multi-input multi-output (MIMO) network are provided. The BS stores resource allocation information about the MIMO network and an SS list, and generate a super frame according to the resource allocation information and the SS list. The super frame comprises a pilot pattern which comprises a plurality of pilots and data. The BS and SS both considers the pilot pattern as an identifier of the SS. When there are communications occurred between the BS and the SS, the BS/SS will confirm whether the pilot pattern of the super frame matches the identifier of the SS to reduce interference from other stations in the MIMO network.

Abstract: A base station (BS), a subordinated station (SS) and the transmission methods thereof for use in a multi-input multi-output (MIMO) network are provided. The BS stores resource allocation information about the MIMO network and an SS list, and generate a super frame according to the resource allocation information and the SS list. The super frame comprises a pilot pattern which comprises a plurality of pilots and data. The BS and SS both considers the pilot pattern as an identifier of the SS. When there are communications occurred between the BS and the SS, the BS/SS will confirm whether the pilot pattern of the super frame matches the identifier of the SS to reduce interference from other stations in the MIMO network.

Abstract: A base station (BS), a subordinated station (SS) and the transmission methods thereof for use in a multi-input multi-output (MIMO) network are provided. The BS stores resource allocation information about the MIMO network and an SS list, and generate a super frame according to the resource allocation information and the SS list. The super frame comprises a pilot pattern which comprises a plurality of pilots and data. The BS and SS both considers the pilot pattern as an identifier of the SS. When there are communications occurred between the BS and the SS, the BS/SS will confirm whether the pilot pattern of the super frame matches the identifier of the SS to reduce interference from other stations in the MIMO network.