Abstract: A pixel circuit and a display device are provided. The pixel circuit is utilized for driving a light emitting diode. The pixel circuit includes a storage capacitor, a selector, a memory device, and a write switch. The storage capacitor is coupled to the light emitting diode. The selector selects a first signal or a second signal to the storage capacitor according to a stored data. The memory device is coupled to the selector. The memory device stores a written data to obtain the stored data. The write switch is coupled to the memory device. The write switch writes in the written data to the memory device while the pixel circuit is in transition of operation modes.

Abstract: A pixel circuit and a display device are provided. The pixel circuit is utilized for driving a light emitting diode. The pixel circuit includes a storage capacitor, a selector, a memory device, and a write switch. The storage capacitor is coupled to the light emitting diode. The selector selects a first signal or a second signal to the storage capacitor according to a stored data. The memory device is coupled to the selector. The memory device stores a written data to obtain the stored data. The write switch is coupled to the memory device. The write switch writes in the written data to the memory device while the pixel circuit is in transition of operation modes.

Abstract: A display device includes a plurality of pixel electrodes arranged in an array. A first switch electrically connected to a first pixel electrode of the pixel electrodes. A second switch electrically connected to a second pixel electrode of the pixel electrodes. The second switch is electrically connected between the first switch and a data line, and the first pixel electrode and the first pixel electrode are respectively located at two row of the pixel electrodes that are not adjacent to each other.

Abstract: A display device comprises a plurality of pixel unit sets and a plurality of common electrode (VCOM) signal generation circuits. Each of the pixel unit sets comprises a first portion pixel unit and a second portion pixel unit. Each of the first portion pixel unit and each of the second portion pixel unit comprise a plurality rows of pixel units. Each row of the pixel units comprises a plurality of pixel units. The VCOM signal generation circuits are respectively coupled to one of the pixel unit sets. The VCOM signal generation circuits are divided into a plurality of groups of number m. The VCOM signal generation circuits in each of the groups generate a first VCOM signal and a second VCOM signal to the coupled pixel unit set according to a first clock signal, a second clock signal and one of a plurality control signal sets of number m.

Abstract: A display device comprises a plurality of pixel unit sets and a plurality of common electrode (VCOM) signal generation circuits. Each of the pixel unit sets comprises a first portion pixel unit and a second portion pixel unit. Each of the first portion pixel unit and each of the second portion pixel unit comprise a plurality rows of pixel units. Each row of the pixel units comprises a plurality of pixel units. The VCOM signal generation circuits are respectively coupled to one of the pixel unit sets. The VCOM signal generation circuits are divided into a plurality of groups of number m. The VCOM signal generation circuits in each of the groups generate a first VCOM signal and a second VCOM signal to the coupled pixel unit set according to a first clock signal, a second clock signal and one of a plurality control signal sets of number m.

Abstract: A display apparatus including a display panel and a plurality of common voltage generators is provided. The display panel has a plurality of pixel regions. The plurality of common voltage generators are coupled to the plurality of pixel regions respectively and generate a plurality of common voltages, wherein each of the plurality of common voltage generators respectively maintains each of the plurality of common voltages at a first voltage, a second voltage, and a third voltage in a plurality of first timing periods in a first polarity period and respectively maintains each of the plurality of common voltages at a fifth voltage, a fourth voltage, and the third voltage in a plurality of second timing periods in a second polarity period in a narrow view mode, wherein the first voltage>the second voltage>the third voltage>the fourth voltage>the fifth voltage.

Abstract: A display device includes a plurality of scan lines, a plurality of data lines, a plurality of pixel units, a plurality of gate driving circuits, and a plurality of connection lines. The scan lines extend in a first direction. The data lines extend in a second direction. The gate driving circuits extend in the first direction, and each of the gate driving circuits crosses through at least two of the pixel units. At least two gate driving circuits are included between two adjacent rows of the pixel units. The connection lines extend in the second direction and are electrically connected to the gate driving circuits. At least part of the connection lines overlap the data lines. The connection lines include a plurality of output lines and a plurality of signal lines. The output lines are electrically connected to the scan lines.

Abstract: A display device includes a plurality of pixel electrodes arranged in an array. A first switch electrically connected to a first pixel electrode of the pixel electrodes. A second switch electrically connected to a second pixel electrode of the pixel electrodes. The second switch is electrically connected between the first switch and a data line, and the first pixel electrode and the first pixel electrode are respectively located at two row of the pixel electrodes that are not adjacent to each other.

Abstract: A display apparatus including a display panel and a plurality of common voltage generators is provided. The display panel has a plurality of pixel regions. The plurality of common voltage generators are coupled to the plurality of pixel regions respectively and generate a plurality of common voltages, wherein each of the plurality of common voltage generators respectively maintains each of the plurality of common voltages at a first voltage, a second voltage, and a third voltage in a plurality of first timing periods in a first polarity period and respectively maintains each of the plurality of common voltages at a fifth voltage, a fourth voltage, and the third voltage in a plurality of second timing periods in a second polarity period in a narrow view mode, wherein the first voltage>the second voltage>the third voltage>the fourth voltage>the fifth voltage.

Abstract: A display device includes a plurality of scan lines, a plurality of data lines, a plurality of pixel units, a plurality of gate driving circuits, and a plurality of connection lines. The scan lines extend in a first direction. The data lines extend in a second direction. The gate driving circuits extend in the first direction, and each of the gate driving circuits crosses through at least two of the pixel units. At least two gate driving circuits are included between two adjacent rows of the pixel units. The connection lines extend in the second direction and are electrically connected to the gate driving circuits. At least part of the connection lines overlap the data lines. The connection lines include a plurality of output lines and a plurality of signal lines. The output lines are electrically connected to the scan lines.

Abstract: A display panel, a gate driver and a control method are disclosed herein. The gate driver includes series-coupled driving stages. One of the driving stages includes an input unit and a shift register circuit. The input unit outputs a shift signal to a control node according to a gate driving signal from the previous driving stage and the gate driving signal from the next driving stage. The shift register circuit is electrically coupled to the control node, and outputs the gate driving signal. During the enabling period of the gate driving signal from the previous driving stage and the enabling period of the gate driving signal from the current driving stage, the shift register circuit keeps the voltage level of the control node being at a first voltage.

Abstract: A shift register has a first switch, a pull-up circuit, and a pull-down circuit. The first switch receives a first clock signal. The pull-up circuit is configured to turn on the first switch to pull up a voltage level of an output terminal of the shift register. The pull-up circuit has a second switch and a first control circuit. The first control circuit is coupled to a first system power terminal to avoid an excessive voltage difference between two nodes of the first control circuit. The pull-down circuit is configured to pull down the voltage level of the output terminal of the shift register when the first switch is turned off, and further configured to keep a voltage level of a control node of a switch coupled between the output terminal and a second system power terminal at a low voltage.

Abstract: A shift register has an input stage circuit, a first switch, a control circuit and a pull down circuit. A first end of the first switch receives a first clock signal. A second end and a control end of the first switch are respectively coupled to an output end of the shift register and a first output end of the input stage circuit. The control circuit controls electrical connection between a first power terminal and a node according to a second clock signal and controls electrical connection between the node and a second power terminal according to a voltage level of a second output end of the input stage circuit. The pull down circuit controls electrical connection between the second output end and the second power terminal and electrical connection between the output end and the second power terminal according to a voltage level of the node.

Abstract: A flat display panel includes a plurality of gate lines, a plurality of data lines, a plurality of tracking gate lines and a display area. The display area is disposed with pixel modules therein. Each pixel module includes a first pixel unit and a second pixel unit. The first pixel unit is configured to determine whether to receive a data transmitted on the first predetermined data line according to a voltage level of the first predetermined gate line. The second pixel unit is configured to determine whether to receive a voltage level of the second predetermined gate line according to a voltage level of the first predetermined gate line and determine whether to receive a data from the first pixel unit according to a voltage level received from the second predetermined gate line.

Abstract: A liquid crystal display panel includes a pixel array, a first shift register, M first output cells, a second shift register, and N second output cells. The first register is disposed on a first side of the pixel array. The M first output cells are coupled to and next to the first shift register for providing M gate signals to M rows of the pixel array according to a first clock signal. The second register is disposed on a second side of the pixel array. The N second output cells are coupled to and next to the second shift register for providing N gate signals to N rows of the pixel array according to a second clock signal. M and N are positive integers.

Abstract: A flat display panel includes a plurality of gate lines, a plurality of data lines, a plurality of tracking gate lines and a display area. The display area is disposed with pixel modules therein. Each pixel module includes a first pixel unit and a second pixel unit. The first pixel unit is configured to determine whether to receive a data transmitted on the first predetermined data line according to a voltage level of the first predetermined gate line. The second pixel unit is configured to determine whether to receive a voltage level of the second predetermined gate line according to a voltage level of the first predetermined gate line and determine whether to receive a data from the first pixel unit according to a voltage level received from the second predetermined gate line.

Abstract: A display panel, a gate driver and a control method are disclosed herein. The gate driver includes series-coupled driving stages. One of the driving stages includes an input unit and a shift register circuit. The input unit outputs a shift signal to a control node according to a gate driving signal from the previous driving stage and the gate driving signal from the next driving stage. The shift register circuit is electrically coupled to the control node, and outputs the gate driving signal. During the enabling period of the gate driving signal from the previous driving stage and the enabling period of the gate driving signal from the current driving stage, the shift register circuit keeps the voltage level of the control node being at a first voltage.

Abstract: A shift register has a first switch, a pull-up circuit, and a pull-down circuit. The first switch receives a first clock signal. The pull-up circuit is configured to turn on the first switch to pull up a voltage level of an output terminal of the shift register. The pull-up circuit has a second switch and a first control circuit. The first control circuit is coupled to a first system power terminal to avoid an excessive voltage difference between two nodes of the first control circuit. The pull-down circuit is configured to pull down the voltage level of the output terminal of the shift register when the first switch is turned off, and further configured to keep a voltage level of a control node of a switch coupled between the output terminal and a second system power terminal at a low voltage.

Abstract: A shift register has an input stage circuit, a first switch, a control circuit and a pull down circuit. A first end of the first switch receives a first clock signal. A second end and a control end of the first switch are respectively coupled to an output end of the shift register and a first output end of the input stage circuit. The control circuit controls electrical connection between a first power terminal and a node according to a second clock signal and controls electrical connection between the node and a second power terminal according to a voltage level of a second output end of the input stage circuit. The pull down circuit controls electrical connection between the second output end and the second power terminal and electrical connection between the output end and the second power terminal according to a voltage level of the node.

Abstract: A liquid crystal display panel includes a pixel array, a first shift register, M first output cells, a second shift register, and N second output cells. The first register is disposed on a first side of the pixel array. The M first output cells are coupled to and next to the first shift register for providing M gate signals to M rows of the pixel array according to a first clock signal. The second register is disposed on a second side of the pixel array. The N second output cells are coupled to and next to the second shift register for providing N gate signals to N rows of the pixel array according to a second clock signal. M and N are positive integers.