Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an isolation layer over a substrate. The method includes forming a spacer layer over the first fin, the second fin, and the isolation layer. The method includes forming a gate dielectric layer in the first trench and covering the first fin, the second fin, and the isolation layer exposed by the first trench. The method includes partially removing the gate dielectric layer to form a second trench in the gate dielectric layer and between the first fin and the second fin. The method includes forming a gate electrode in the first trench of the spacer layer and over the gate dielectric layer.

Abstract: A semiconductor device includes a semiconductor substrate having a first lattice constant, a dopant blocking layer disposed over the semiconductor substrate, the dopant blocking layer having a second lattice constant different from the first lattice constant, and a buffer layer disposed over the dopant blocking layer, the buffer layer having a third lattice constant different from the second lattice constant. The semiconductor device also includes a plurality of channel members suspended over the buffer layer, an epitaxial feature abutting the channel members, and a gate structure wrapping each of the channel members.

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a first dielectric fin and a second dielectric fin over a substrate, and the second dielectric fin is taller than the first dielectric fin. The method also includes forming a gate stack over the substrate, and the gate stack extends across the first dielectric fin and the second dielectric fin. The method further includes partially removing the gate stack such that an opening exposing the second dielectric fin is formed and forming an isolation structure in the opening.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes first and second gate structures formed over a semiconductor substrate and a multilayer gate isolation structure separating the first gate structure from the second gate structure. The multilayer gate isolation structure includes a first insulating feature adjacent to upper portions of the first gate structure and the second gate structure, and a second insulating feature separating the semiconductor substrate from the first insulating feature. The material of the second insulating feature is different than that of the first insulating feature. The second insulating feature has a lower dielectric constant or lower etch resistance than the first insulating feature.

Abstract: A dummy fin described herein includes a low dielectric constant (low-k or LK) material outer shell. A leakage path that would otherwise occur due to a void being formed in the low-k material outer shell is filled with a high dielectric constant (high-k or HK) material inner core. This increases the effectiveness of the dummy fin to provide electrical isolation and increases device performance of a semiconductor device in which the dummy fin is included. Moreover, the dummy fin described herein may not suffer from bending issues experienced in other types of dummy fins, which may otherwise cause high-k induced alternating current (AC) performance degradation. The processes for forming the dummy fins described herein are compatible with other fin field effect transistor (finFET) formation processes and are be easily integrated to minimize and/or prevent polishing issues, etch back issues, and/or other types of semiconductor processing issues.

Abstract: A dummy fin described herein includes a low dielectric constant (low-k or LK) material outer shell. A leakage path that would otherwise occur due to a void being formed in the low-k material outer shell is filled with a high dielectric constant (high-k or HK) material inner core. This increases the effectiveness of the dummy fin to provide electrical isolation and increases device performance of a semiconductor device in which the dummy fin is included. Moreover, the dummy fin described herein may not suffer from bending issues experienced in other types of dummy fins, which may otherwise cause high-k induced alternating current (AC) performance degradation. The processes for forming the dummy fins described herein are compatible with other fin field effect transistor (finFET) formation processes and are be easily integrated to minimize and/or prevent polishing issues, etch back issues, and/or other types of semiconductor processing issues.

Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

Abstract: Charge storage and sensing devices having a tunnel diode operable to sense charges stored in a charge storage structure are provided. In some embodiments, a device includes a substrate, a charge storage device on the substrate, and tunnel diode on the substrate adjacent to the charge storage device. The tunnel diode includes a tunnel diode dielectric layer on the substrate, and a tunnel diode electrode on the tunnel diode dielectric layer. A substrate electrode is disposed on the doped region of the substrate, and the tunnel diode electrode is positioned between the charge storage device and the substrate electrode.

Abstract: A dummy fin described herein includes a low dielectric constant (low-k or LK) material outer shell. A leakage path that would otherwise occur due to a void being formed in the low-k material outer shell is filled with a high dielectric constant (high-k or HK) material inner core. This increases the effectiveness of the dummy fin to provide electrical isolation and increases device performance of a semiconductor device in which the dummy fin is included. Moreover, the dummy fin described herein may not suffer from bending issues experienced in other types of dummy fins, which may otherwise cause high-k induced alternating current (AC) performance degradation. The processes for forming the dummy fins described herein are compatible with other fin field effect transistor (finFET) formation processes and are be easily integrated to minimize and/or prevent polishing issues, etch back issues, and/or other types of semiconductor processing issues.

Abstract: A semiconductor device includes a semiconductor substrate having a first lattice constant, a dopant blocking layer disposed over the semiconductor substrate, the dopant blocking layer having a second lattice constant different from the first lattice constant, and a buffer layer disposed over the dopant blocking layer, the buffer layer having a third lattice constant different from the second lattice constant. The semiconductor device also includes a plurality of channel members suspended over the buffer layer, an epitaxial feature abutting the channel members, and a gate structure wrapping each of the channel members.

Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

Abstract: A method includes providing a semiconductor substrate; epitaxially growing a blocking layer from a top surface of the semiconductor substrate, wherein the blocking layer has a lattice constant different from the semiconductor substrate; epitaxially growing a semiconductor layer above the blocking layer; patterning the semiconductor layer to form a semiconductor fin, wherein the blocking layer is under the semiconductor fin; forming a source/drain (S/D) feature in contact with the semiconductor fin; and forming a gate structure engaging the semiconductor fin.

Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

Abstract: Charge storage and sensing devices having a tunnel diode operable to sense charges stored in a charge storage structure are provided. In some embodiments, a device includes a substrate, a charge storage device on the substrate, and tunnel diode on the substrate adjacent to the charge storage device. The tunnel diode includes a tunnel diode dielectric layer on the substrate, and a tunnel diode electrode on the tunnel diode dielectric layer. A substrate electrode is disposed on the doped region of the substrate, and the tunnel diode electrode is positioned between the charge storage device and the substrate electrode.

Abstract: A method includes providing a semiconductor substrate; epitaxially growing a blocking layer from a top surface of the semiconductor substrate, wherein the blocking layer has a lattice constant different from the semiconductor substrate; epitaxially growing a semiconductor layer above the blocking layer; patterning the semiconductor layer to form a semiconductor fin, wherein the blocking layer is under the semiconductor fin; forming a source/drain (S/D) feature in contact with the semiconductor fin; and forming a gate structure engaging the semiconductor fin.

Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

Abstract: A method of fabricating a semiconductor device includes forming a dummy gate structure on a substrate, forming gate spacers on sidewalls of the dummy gate structure, and depositing an interlayer dielectric layer around the gate spacers. The method also includes removing the dummy gate structure to form a space between the gate spacers, and forming a gate structure in the space, wherein the gate structure includes a gate dielectric layer and a gate electrode layer over the gate dielectric layer. The method further includes removing a portion of the gate electrode layer to form a recess that is surrounded by the gate dielectric layer. In addition, the method includes implanting on the interlayer dielectric layer to form a strained layer for bending the gate dielectric layer and the gate spacers towards the recess.

Abstract: Charge storage and sensing devices having a tunnel diode operable to sense charges stored in a charge storage structure are provided. In some embodiments, a device includes a substrate, a charge storage device on the substrate, and tunnel diode on the substrate adjacent to the charge storage device. The tunnel diode includes a tunnel diode dielectric layer on the substrate, and a tunnel diode electrode on the tunnel diode dielectric layer. A substrate electrode is disposed on the doped region of the substrate, and the tunnel diode electrode is positioned between the charge storage device and the substrate electrode.

Abstract: A semiconductor device includes a substrate, a gate stack over the substrate, an insulating structure over the gate stack, a conductive via in the insulating structure, and an contact etch stop layer (CESL) over the insulating structure. The insulating structure has an air slit therein. The conductive via is electrically connected to the gate stack. A portion of the CESL is exposed in the air slit.