Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an isolation layer over a substrate. The method includes forming a spacer layer over the first fin, the second fin, and the isolation layer. The method includes forming a gate dielectric layer in the first trench and covering the first fin, the second fin, and the isolation layer exposed by the first trench. The method includes partially removing the gate dielectric layer to form a second trench in the gate dielectric layer and between the first fin and the second fin. The method includes forming a gate electrode in the first trench of the spacer layer and over the gate dielectric layer.

Abstract: A method for detecting an abnormal occurrence of an application program includes a feature parameter collected according to the log data of at least one application program. The feature parameter is inputted into a first and a second prediction model and a first and a second detection model, and the feature parameter is calculated based on the first and the second prediction model and the first and the second detection model to respectively generate a first and a second prediction value and a first and a second detection value. The first and the second prediction value and the first and the second detection value are respectively weighted based on an abnormal score evaluation equation to generate an abnormal evaluation value of the application program. Finally, the abnormal evaluation value is inputted into a warning ranking model to rank the abnormal evaluation value, generating the corresponding warning signal.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium, and an apparatus for debugging a solid-state disk (SSD) device. The method is performed by a processing unit of a single-board personal computer (PC) to include: simulating to issue a first Joint Test Action Group (JTAG) command through a General-Purpose Input/Output (GPIO) interface (I/F) to the SSD device for stopping a running of a processing unit of a flash controller in the SSD device; simulating to issue a second JTAG command through the GPIO I/F to the SSD device for forcing the SSD device to exit a sleep mode; and simulating to issue a third JTAG command through the GPIO I/F to the SSD device for reading a designated length of data from a static random access memory (SRAM) in the SSD device.

Abstract: An equalizer control method is provided, where the method may write a plurality of parameters into a programmable filter pattern register file of a receiver to set up the programmable filter pattern register file. The receiver includes a plurality of equalization settings for selection, and the method may further perform selection between the equalization settings of the receiver according to the parameters of the programmable filter pattern register file and a signal sequence received by the receiver. An associated equalizer control apparatus is also provided, where the equalizer control apparatus is disposed in a receiver. The receiver includes a plurality of equalization settings, and the equalizer control apparatus applies the equalizer control method to perform selection between the equalization settings of the receiver.

Abstract: A method for sending a keycode of a non-keyboard apparatus is provided and includes the following steps. The non-keyboard apparatus determines the connection status between itself and a computer by the time required for device enumeration. Then, according to a value generated from device enumeration, the non-keyboard apparatus identifies the kind of operating system running on the computer. The non-keyboard apparatus sends to the computer a keycode corresponding to the Num Lock key and/or a keycode corresponding to the Caps Lock key such that a sending time and a feedback time are obtained. A parameter related to the efficiency of the computer is then calculated based.

Abstract: An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M1), wherein the plurality of metal lines couples the plurality of power TSVs to integrated circuit devices on the substrate.

Abstract: An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M1), wherein the plurality of metal lines couples the plurality of power TSVs to integrated circuit devices on the substrate.

Abstract: A through silicon via architecture for integrated circuits is provided. The integrated circuit (IC) includes a substrate with a top surface and a bottom surface with circuitry formed on the top surface, a plurality of bonding pads formed along a periphery of the bottom surface, and a backside metal layer (BML) formed on the bottom surface and electrically coupled to a second subset of bonding pads in the plurality of bonding pads. A first subset of bonding pads in the plurality of bonding pads is electrically coupled to circuitry on the top surface with through silicon vias (TSV). The BML distributes electrical signals provided by the second subset of bonding pads.

Abstract: An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M1), wherein the plurality of metal lines couples the plurality of power TSVs to integrated circuit devices on the substrate.

Abstract: A method for sending a keycode of a non-keyboard apparatus is provided and includes the following steps. The non-keyboard apparatus determines the connection status between itself and a computer by the time required for device enumeration. Then, according to a value generated from device enumeration, the non-keyboard apparatus identifies the kind of operating system running on the computer. The non-keyboard apparatus sends to the computer a keycode corresponding to the Num Lock key and/or a keycode corresponding to the Caps Lock key such that a sending time and a feedback time are obtained. A parameter related to the efficiency of the computer is then calculated based.

Abstract: A through silicon via architecture for integrated circuits is provided. The integrated circuit (IC) includes a substrate with a top surface and a bottom surface with circuitry formed on the top surface, a plurality of bonding pads formed along a periphery of the bottom surface, and a backside metal layer (BML) formed on the bottom surface and electrically coupled to a second subset of bonding pads in the plurality of bonding pads. A first subset of bonding pads in the plurality of bonding pads is electrically coupled to circuitry on the top surface with through silicon vias (TSV). The BML distributes electrical signals provided by the second subset of bonding pads.

Abstract: An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M1), wherein the plurality of metal lines couples the plurality of power TSVs to integrated circuit devices on the substrate.