Abstract: A door locking mechanism and semiconductor container using the same include door panel, cover, and locking module. The door panel has a first stop structure. The cover and the door panel define an accommodating space for receiving the locking module. The locking module includes rotating member, holding member, and elastic member. The elastic member is disposed on the holding member and has a second stop structure near the first stop structure. The elastic member is disposed between the holding and the rotating member. The elastic member is compressed when a force is applied to the holding member, and the second stop structure detaches from a limitation state with the first stop structure for allowing a rotating operation of the rotating member. The elastic member elastically restores when the force is removed, and the second stop structure returns to the limitation state for limiting the rotating operation.

Abstract: A supporting shelf module includes a plurality of plastic supporting plates parallelly arranged in a height direction, and at least one pair of metal-made connectors located at two opposite ends of the supporting plates in the height direction. The connectors in one pair are correspondingly located in two horizontal planes perpendicular to the height direction. A wafer container is also disclosed, which includes a container body having at least two sets of the supporting shelf modules mounted therein, at least two top retaining brackets and at least two bottom retaining grooves provided on an inward side of a top and a bottom panel of the container body, respectively. The supporting shelf module has upper ends engaged with the top retaining brackets and lower ends engaged with and limited to the bottom retaining grooves in an engaging direction. Thus, the tolerance problem of the conventional wafer shelf can be solved.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may establish, by a first subscription of the UE, a connection to a first network entity using two transmit (Tx) chains of the UE. The UE may receive, by a second subscription of the UE, a paging message from a second network entity. The UE may receive, by the first subscription from the second subscription, a request for the first subscription to enter a mode that supports one Tx chain. The UE, by the first subscription, may reduce the two Tx chains to the one Tx chain for the first subscription. The UE may perform, by the second subscription to the second network entity, the connection setup based at least in part on the first subscription reducing the two Tx chains to the one Tx chain. Numerous other aspects are described.

Abstract: Aspects are provided which allow a UE including an application processor and a modem to disable measurements of reference signals from 5G base stations which are inapplicable to EN-DC. The UE may receive a reference signal from a base station. The UE may identify a frequency range. The UE may provide, using the application processor, an indication to the modem. The UE may determine whether to measure the reference signal using the modem based on the indication provided to the modem from the application processor and whether the reference signal is within the identified frequency range and further based on whether the base station is standalone or non-standalone. The UE may refrain from measuring the reference signal in response to the determination. As a result, inter-RAT handovers from LTE base stations to 5G base stations are prevented, UE power consumption is thereby saved, and support for EN-DC is maintained.

Abstract: A manufacturing process for electrode of neuromodulation probe includes the steps of: preparing a plurality of the manufacturing fixtures for electrode of neuromodulation probe; preparing a plurality of the manufacturing fixtures for electrode in a surrounding manner by having the first-layer frames to be externally disposed side by side with the bevels of the two neighboring first-layer frames close to each other, so that the second-layer frames, the plurality of electrodes and the plurality of wires are enclosed thereinside; placing a cylinder amid the plurality of manufacturing fixtures for electrode to have the plurality of wires to surround the cylinder; having a fluid plastic to surround the cylinder by filling all the spaces between the plurality of wires and the plurality of electrodes, and waiting the fluid plastic to cure; removing the plurality of first-layer frames and the plurality of second-layer frames; and, pulling off the cylinder.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, from an application processor associated with the UE, an indication of a traffic service type and whether an uplink data stall has occurred. The UE may detect that one or more threshold criteria are satisfied for a serving cell, wherein a threshold value associated with at least one of the one or more threshold criteria is based at least in part on the traffic service type. The UE may transmit information associated with one or more adjusted measurement values of the serving cell based at least in part on detecting that the one or more threshold criteria are satisfied. Numerous other aspects are described.

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

Abstract: A method of manufacturing a semiconductor device includes forming a gate trench over a semiconductor substrate, depositing a gate dielectric layer and a work function layer in the gate trench, depositing a capping layer over the work function layer, passivating a surface portion of the capping layer to form a passivation layer, removing the passivation layer, depositing a fill layer in the gate trench, recessing the fill layer and the capping layer, and forming a contact metal layer above the capping layer in the gate trench.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.