Patents by Inventor Wei Ching

Wei Ching has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978947
    Abstract: A Rugged portable device comprises: a base, a cover pivotally connected to the base, a first antenna unit, a second antenna unit, and a control unit. The first antenna unit and the second antenna unit are respectively disposed at an edge of the cover and an edge of the base, and the first antenna unit and the second antenna unit respectively have a near-field antenna and a far-field antenna. When the cover pivots relative to the base and is close to the base, the near-field antenna disposed at the cover and the near-field antenna disposed at the base generate a near-field communication (NFC) sensing signal and the near-field communication sensing signal is transmitted to the control unit. Therefore, the control unit sets up one of functions in the rugged portable device. For instance, the control unit switches off and/or switches on the far-field antenna or a peripheral unit (a keyboard or a camera).
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: May 7, 2024
    Assignee: Winmate Inc.
    Inventors: Ku-Ching Lu, Wei-Wen Yang, Hsin-Chin Wang, Chun-Yu Huang
  • Patent number: 11976374
    Abstract: A method and device of removing and recycling metals from a mixing acid solution, includes adsorbing a mixing acid solution with a pH value of ?1 to 4 and a cobalt ion concentration of 100 to 1,000 mg/L by at least two cation resins in series setting to the cobalt ion concentration in the mixing acid solution is less than 10 mg/L, and then adjusting the pH value of the mixing acid solution after adsorption to meet a discharge standard, wherein the particle size of the at least two cation resins in series setting is 150˜1,200 ?m. After the cation resins are saturated by adsorption, regenerating the cation resins by sulfuric acid to form a cobalt sulfate solution, and then electrolytically treating the cobalt sulfate solution to obtain electrolytic cobalt and sulfuric acid electrolyte. The operation process is simple without complicated equipment, and it can effectively recycle metals from mixing acid solutions.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: May 7, 2024
    Assignee: MEGA UNION TECHNOLOGY INCORPORATED
    Inventors: Kuo-Ching Lin, Yung-Cheng Chiang, Shr-Han Shiu, Wei-Rong Tey, Yu-Hsuan Li
  • Patent number: 11978740
    Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Harry-Hak-Lay Chuang, Kuo-Ching Huang, Wei-Cheng Wu, Hsin Fu Lin, Henry Wang, Chien Hung Liu, Tsung-Hao Yeh, Hsien Jung Chen
  • Publication number: 20240145401
    Abstract: The present disclosure provides method to generate a dummy pad pattern. A method according to embodiment of the present disclosure includes receiving a design layout that includes a device region disposed in a scribe line region, identifying a center portion of the scribe line region surrounding the device region and an edge portion surrounding the center portion, dividing the edge portion into a plurality of rectangular areas, super-positioning a dummy pattern on each of the plurality of rectangular areas to obtain edge dummy patterns, super-positioning the dummy pattern on the center portion to obtain center dummy patterns, carving out a portion of the dummy pattern corresponding to the device region from the center dummy patterns to obtain net center dummy patterns, generating a scribe line dummy pattern based on the edge dummy patterns and the net center dummy patterns, and fabricating a first photomask including the scribe line dummy pattern.
    Type: Application
    Filed: May 25, 2023
    Publication date: May 2, 2024
    Inventors: Chang-Ching Yu, Wei-Ti Hsu
  • Publication number: 20240145600
    Abstract: A semiconductor device includes a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode. The gate insulating layer is disposed between the gate electrode and the active layer, the source electrode and the drain electrode are arranged on one side of the gate insulating layer, wherein the gate insulating layer includes multilayer oxide films stacked on each other and at least one interface layer between the multilayer oxide films, and the material of the at least one interface layer is different from the material of the oxide films.
    Type: Application
    Filed: January 20, 2023
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih WEN, Yi-Lin YANG, Hai-Ching CHEN
  • Publication number: 20240145571
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 2, 2024
    Inventors: Po-Ting Lin, Yu-Ming Hsiang, Wei-Chih Wen, Yin-Hao Wu, Wu-Wei Tsai, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 11969089
    Abstract: A slide rail assembly includes a first rail, a second rail, and an auxiliary member. The first rail includes a passage, and the passage includes a passage opening. The second rail is inserts in the passage from the passage opening through being guided by the auxiliary member.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: April 30, 2024
    Assignees: KING SLIDE WORKS CO., LTD., KING SLIDE TECHNOLOGY CO., LTD.
    Inventors: Ken-Ching Chen, Shun-Ho Yang, Wei-Chen Chang, Chun-Chiang Wang
  • Patent number: 11972981
    Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes forming a plurality of fins extending from a substrate. In various embodiments, each of the plurality of fins includes a portion of a substrate, a portion of a first epitaxial layer on the portion of the substrate, and a portion of a second epitaxial layer on the portion of the first epitaxial layer. The portion of the first epitaxial layer of each of the plurality of fins is oxidized, and a liner layer is formed over each of the plurality of fins. Recessed isolation regions are then formed adjacent to the liner layer. The liner layer may then be etched to expose a residual material portion (e.g., Ge residue) adjacent to a bottom surface of the portion of the second epitaxial layer of each of the plurality of fins, and the residual material portion is removed.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Ying-Keung Leung
  • Publication number: 20240134418
    Abstract: An electronic assembly includes an electronic device and an external device. The electronic device includes a main body and a fixing base. The main body includes a first opening. The fixing base includes an upper cover, a cam, a first spring, a button, a second spring, a pedestal, a first retractable hook and a second retractable hook. The first retractable hook includes a first inclined protrusion structure. The second retractable hook includes a second inclined protrusion structure. The external device includes a bracket. The bracket includes a first insertion piece and a second insertion piece. The first insertion piece includes a seventh opening. The second insertion piece includes an eighth opening. The first insertion piece and the second insertion piece are penetrated through the first opening. The first inclined protrusion structure is inserted into the seventh opening. The second inclined protrusion structure is inserted into the eighth opening.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 25, 2024
    Inventors: Wei-Ching Kuo, Rong-Fu Lee
  • Publication number: 20240132496
    Abstract: An ionic compound, an absorbent and an absorption device are provided. The ionic compound has a structure represented by Formula (I): ABn, ??Formula (I) wherein A is B is R1, R2, R3, R4, R5, and R6 are independently H, C1-6 alkyl group; and n is 1 or 2.
    Type: Application
    Filed: June 9, 2023
    Publication date: April 25, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Wei-Chih LEE, Yi-Hsiang CHEN, Chih-Hao CHEN, Ai-Yu LIOU, Jyi-Ching PERNG, Jiun-Jen CHEN
  • Publication number: 20240136346
    Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
    Type: Application
    Filed: April 17, 2023
    Publication date: April 25, 2024
    Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
  • Publication number: 20240122342
    Abstract: A slide rail assembly includes a first rail, a second rail, a slide-facilitating device, and a working member. The second rail is movably mounted in a channel of, and is displaceable with respect to, the first rail. The slide-facilitating device is movably mounted between the rails and includes an engaging feature. The working member is provided on the first rail and includes a main body portion, an elastic portion for supporting the main body portion, and a predetermined portion connected to the main body portion. The first rail includes a supporting portion for supporting the elastic portion of the working member. The engaging feature is engaged with the predetermined portion of the working member when the slide-facilitating device is at a predetermined position.
    Type: Application
    Filed: March 27, 2023
    Publication date: April 18, 2024
    Inventors: Ken-Ching CHEN, Shun-Ho YANG, Wei-Chen CHANG, Chun-Chiang WANG
  • Publication number: 20240128376
    Abstract: A device a includes a substrate, two source/drain (S/D) features over the substrate, and semiconductor layers suspended over the substrate and connecting the two S/D features. The device further includes a dielectric layer disposed between two adjacent layers of the semiconductor layers and an air gap between the dielectric layer and one of the S/D features, where a ratio between a length of the air gap to a thickness of the first dielectric layer is in a range of 0.1 to 1.0.
    Type: Application
    Filed: December 26, 2023
    Publication date: April 18, 2024
    Inventors: Shih-Chiang Chen, Wei-Yang Lee, Chia-Pin Lin, Yuan-Ching Peng
  • Publication number: 20240129291
    Abstract: The invention discloses a method to set up a cross-domain DDS-secure network and then use it to transmit various kinds of data. To set up the cross-domain DDS-secure network, we first register IoT and monitor devices on the administration website. Second, we group devices based on our needs and then ask the website to generate configurations and certificates for each device. Finally, we download those files and deploy them to each device. In an extremely case, we can accomplish all operations only through a mobile device. During the system operating, all devices establish the DDS-secure connections to each other, and data will transmit on the network securely.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 18, 2024
    Inventors: Tsung-Che Tsai, Wei-Sheng Chen, Hsi-Ching Lin
  • Patent number: 11961912
    Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-An Lin, Wei-Yuan Lu, Feng-Cheng Yang, Tzu-Ching Lin, Li-Li Su
  • Publication number: 20240115043
    Abstract: A slide rail assembly includes a first rail, a second rail, a slide-facilitating device, and a retaining member. The second rail is movably mounted in a channel of, and is longitudinally displaceable with respect to, the first rail. The slide-facilitating device is movably mounted between the rails and includes an engaging feature. The retaining member is provided on the first rail and includes an elastic portion with a predetermined feature. The first rail includes a limiting feature for preventing deformation of the elastic portion. When the second rail is moved out of the channel after displacement in an opening direction with respect to the first rail, the slide-facilitating device is at a predetermined position, with the engaging feature engaged with the predetermined feature.
    Type: Application
    Filed: March 27, 2023
    Publication date: April 11, 2024
    Inventors: KEN-CHING CHEN, SHUN-HO YANG, WEI-CHEN CHANG, CHUN-CHIANG WANG
  • Publication number: 20240115457
    Abstract: A health care device and a health care method are illustrated, the health care method is used to arrange the health care device at a predetermined location in front of a belly button of a user with a predetermined distance, and to emit the low-frequency wave with a predetermined frequency to the belly button by using a low-frequency wave emitter. The health care device is formed by the low-frequency wave emitter and a cone/pyramid part. The predetermined frequency is 1.27 Hz to 1.81 Hz, and the predetermined distance is 5 cm to 8 cm. The above health care device and method can increase contents of active T cells and B cells in blood and increase an ability of NK cell strains for poisoning cancer cell strains (K562). In short, the above health care device and method have health benefits without a risk of excessive energy causing harm.
    Type: Application
    Filed: November 23, 2022
    Publication date: April 11, 2024
    Inventors: MING-SHUN LEE, CHIN-SUNG TSENG, HSU-HUI TSENG, HSIEN-CHING TSENG, WEI-LONG LEE
  • Publication number: 20240117037
    Abstract: The invention provides anti-TIGIT (T-cell immunoreceptor with Ig and ITIM domains) antibodies and methods of using the same.
    Type: Application
    Filed: June 30, 2023
    Publication date: April 11, 2024
    Inventors: Jane L. GROGAN, Robert J. JOHNSTON, Yan WU, Wei-Ching LIANG, Patrick LUPARDUS, Mahesh YADAV, Dhaya SESHASAYEE, Meredith HAZEN
  • Publication number: 20240113201
    Abstract: Methods and structures for modulating an inner spacer profile include providing a fin having an epitaxial layer stack including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing the plurality of dummy layers to form a first gap between adjacent semiconductor channel layers of the plurality of semiconductor channel layers. Thereafter, in some examples, the method includes conformally depositing a dielectric layer to substantially fill the first gap between the adjacent semiconductor channel layers. In some cases, the method further includes etching exposed lateral surfaces of the dielectric layer to form an etched-back dielectric layer that defines substantially V-shaped recesses. In some embodiments, the method further includes forming a substantially V-shaped inner spacer within the substantially V-shaped recesses.
    Type: Application
    Filed: January 25, 2023
    Publication date: April 4, 2024
    Inventors: Chih-Ching WANG, Wei-Yang LEE, Bo-Yu LAI, Chung-I YANG, Sung-En LIN
  • Patent number: 11948970
    Abstract: A semiconductor device includes a semiconductor fin, a gate structure, and a dielectric isolation plug. The semiconductor fin extends along a first direction above a substrate and includes a silicon germanium layer and a silicon layer over the silicon germanium layer. The gate structure extends across the semiconductor fin along a second direction perpendicular to the first direction. The dielectric isolation plug extends downwardly from a top surface of the silicon layer into the silicon germanium layer when viewed in a cross section taken along the first direction.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang