Abstract: A system and a method for workplace safety management are provided. The method includes: dividing a work field corresponding to the workplace into work zones; assigning an environmental indicator to each of the work zones according to environmental data of the workplace; generating AR warning image signals according to the work zones and the environmental indicator; transmitting the AR warning image signals respectively to wearable electronic devices located in the workplace; and each of the wearable electronic devices displaying an AR warning image according to the received AR warning image signal.

Abstract: The present disclosure provides a privacy computing method based on homomorphic encryption, which includes steps as follows. The ciphertext data is received, where the ciphertext data has a floating-point homomorphic encryption data structure, and the floating-point homomorphic encryption data structure of the ciphertext data includes the ciphertext mantissa, exponent parameter and gain parameter. The gain parameter sets the precision of the floating point corresponding to the ciphertext mantissa. The exponent parameter is adapted to multiplication or division. The artificial intelligence model performs operations on the ciphertext data to return the ciphertext result.

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.

Abstract: A semiconductor device includes a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode. The gate insulating layer is disposed between the gate electrode and the active layer, the source electrode and the drain electrode are arranged on one side of the gate insulating layer, wherein the gate insulating layer includes multilayer oxide films stacked on each other and at least one interface layer between the multilayer oxide films, and the material of the at least one interface layer is different from the material of the oxide films.

Abstract: A slide rail assembly includes a first rail, a second rail, and an auxiliary member. The first rail includes a passage, and the passage includes a passage opening. The second rail is inserts in the passage from the passage opening through being guided by the auxiliary member.

Abstract: An ionic compound, an absorbent and an absorption device are provided. The ionic compound has a structure represented by Formula (I): ABn, ??Formula (I) wherein A is B is R1, R2, R3, R4, R5, and R6 are independently H, C1-6 alkyl group; and n is 1 or 2.

Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: A device a includes a substrate, two source/drain (S/D) features over the substrate, and semiconductor layers suspended over the substrate and connecting the two S/D features. The device further includes a dielectric layer disposed between two adjacent layers of the semiconductor layers and an air gap between the dielectric layer and one of the S/D features, where a ratio between a length of the air gap to a thickness of the first dielectric layer is in a range of 0.1 to 1.0.

Abstract: A slide rail assembly includes a first rail, a second rail, a slide-facilitating device, and a working member. The second rail is movably mounted in a channel of, and is displaceable with respect to, the first rail. The slide-facilitating device is movably mounted between the rails and includes an engaging feature. The working member is provided on the first rail and includes a main body portion, an elastic portion for supporting the main body portion, and a predetermined portion connected to the main body portion. The first rail includes a supporting portion for supporting the elastic portion of the working member. The engaging feature is engaged with the predetermined portion of the working member when the slide-facilitating device is at a predetermined position.

Abstract: The invention discloses a method to set up a cross-domain DDS-secure network and then use it to transmit various kinds of data. To set up the cross-domain DDS-secure network, we first register IoT and monitor devices on the administration website. Second, we group devices based on our needs and then ask the website to generate configurations and certificates for each device. Finally, we download those files and deploy them to each device. In an extremely case, we can accomplish all operations only through a mobile device. During the system operating, all devices establish the DDS-secure connections to each other, and data will transmit on the network securely.

Abstract: A slide rail assembly includes a first rail, a second rail, a slide-facilitating device, and a retaining member. The second rail is movably mounted in a channel of, and is longitudinally displaceable with respect to, the first rail. The slide-facilitating device is movably mounted between the rails and includes an engaging feature. The retaining member is provided on the first rail and includes an elastic portion with a predetermined feature. The first rail includes a limiting feature for preventing deformation of the elastic portion. When the second rail is moved out of the channel after displacement in an opening direction with respect to the first rail, the slide-facilitating device is at a predetermined position, with the engaging feature engaged with the predetermined feature.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.

Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.

Abstract: An acoustic wave element includes: a substrate; a bonding structure on the substrate; a support layer on the bonding structure; a first electrode including a lower surface on the support layer; a cavity positioned between the support layer and the first electrode and exposing a lower surface of the first electrode; a piezoelectric layer on the first electrode; and a second electrode on the piezoelectric layer, wherein at least one of the first electrode and the second electrode includes a first layer and a second layer that the first layer has a first acoustic impedance and a first electrical impedance, the second layer has a second acoustic impedance and a second electrical impedance, wherein the first acoustic impedance is higher than the second acoustic impedance, and the second electrical impedance is lower than the first electrical impedance.

Abstract: A method includes implanting impurities in a semiconductor substrate to form an etch stop region within the semiconductor substrate; forming a transistor structure on a front side of the semiconductor substrate; forming a front-side interconnect structure over the transistor structure; performing a thinning process on a back side of the semiconductor substrate to reduce a thickness of the semiconductor substrate, wherein the thinning process is slowed by the etch stop region; and forming a back-side interconnect structure over the back side of the semiconductor substrate.

Abstract: The federated learning system includes a moderator and client devices. Each client device performs a method for verifying model update as follows: receiving a hash function and a general model; training a client model according to the general model and raw data; calculating a difference as an update parameter between the general model and the client model, sending the update parameter to the moderator; inputting the update parameter to the hash function to generate a hash value; sending the hash value to other client devices, and receiving other hash values; summing all the hash values to generate a trust value; receiving an aggregation parameter calculated according to the update parameters; inputting the aggregation parameter to the hash function to generate a to-be-verified value; and updating the client model according to the aggregation parameter when the to-be-verified value equals the trust value.

Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

Abstract: A virtual reality shopping system is composed of a login page, a character configuration and selection page, and a virtual reality shopping page. The login page is configured as a system for acknowledging or adding members. After a basic buyer character is chosen, the character configuration and selection page can provide a buyer for performing a modeling to the virtual character. The virtual reality shopping page is designed as a virtual reality three-dimensional shopping website enabling individual buyers to mutually interact by assembling virtual map files, according to the design of virtual reality map files and the interaction with a plurality of virtual characters in the map files. In addition, the virtual characters can fit on virtual clothes or accessories in advance, when performing an Internet transaction on the virtual reality shopping website.