Patents by Inventor Wei-Chou Hsu
Wei-Chou Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8692235Abstract: An organic photoelectric semiconductor device including organic group VA salts in an organic salt-containing layer and a method for manufacturing the same are provided. The organic photoelectric semiconductor device includes: a first electrode; an organic active layer disposed over the first electrode; an organic salt-containing layer disposed over the organic active layer, where the organic salt-containing layer includes quaternary group VA salts of cations represented by the following formula (I) or derivatives thereof and anions; and a second electrode, disposed over the organic salt-containing layer, where, X, R1, R2, R3 and R4 are defined the same as the specification. Accordingly, the present invention can enhance the transmission of electrons and thus enhances the performance of devices.Type: GrantFiled: March 18, 2011Date of Patent: April 8, 2014Assignee: National Cheng Kung UniversityInventors: Ten-Chin Wen, Sung-Nien Hsieh, Tzung-Fang Guo, Wei-Chou Hsu, Chen-Yan Li
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Publication number: 20110227047Abstract: An organic photoelectric semiconductor device including organic group VA salts in an organic salt-containing layer and a method for manufacturing the same are provided. The organic photoelectric semiconductor device includes: a first electrode; an organic active layer disposed over the first electrode; an organic salt-containing layer disposed over the organic active layer, where the organic salt-containing layer includes quaternary group VA salts of cations represented by the following formula (I) or derivatives thereof and anions; and a second electrode, disposed over the organic salt-containing layer, where, X, R1, R2, R3 and R4 are defined the same as the specification. Accordingly, the present invention can enhance the transmission of electrons and thus enhances the performance of devices.Type: ApplicationFiled: March 18, 2011Publication date: September 22, 2011Applicant: National Cheng Kung UniversityInventors: Ten-Chin Wen, Sung-Nien Hsieh, Tzung-Fang Guo, Wei-Chou Hsu, Chen-Yan Li
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Publication number: 20070200142Abstract: The present invention relates to a high linear enhancement-mode heterostructure field-effect transistor. More, the present invention uses an InGaAs channel structure with a linear change, and integrates an adjusting effect of working region corresponding to the threshold voltage of the element. It not only directly provides a complementary structure for the conventional depletion-mode element to select, but also increases the range of the gate voltage swing. More, some important characteristics, such as current driving capacity, transconductance gain, linear amplification, and high speed operation can be largely improved. More particularly, E-mode working element has a low static power. Further, the present invention also has a high stop frequency characteristic of the high speed element from the composite semiconductor, and it can be applied to the microwave push-pull amplification circuit.Type: ApplicationFiled: February 24, 2006Publication date: August 30, 2007Inventors: Ching-Sung Lee, Wei-Chou Hsu, Jun-Chin Huang, Chien-Hung Chen
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Patent number: 6953955Abstract: An InGaAs/GaAs High Electron Mobility Transistor (HEMT) comprises a buffer layer, a main conducting channel, an InGaAs/GaAs thickness-graded superlattice structure, a mono atom ?-doped carrier supply layer, a Schottky cap layer of gate electrode and an Ohmic cap layer of drain electrode and source electrode which are formed successively on a substrate. The superlattice structure comprises spacer and sub-channel. By using thickness-graded superlattice spacer structure is able to ameliorate lattice-mismatch-induced scattering within heterostucture interfacial, increase range of gate voltage swing in gate electrode, and through real-space transfer generated by bias voltage in high electric field, drain-to-source saturation current proceed step-up phenomenon to forming a HEMT having scalable voltage multi-extrinsic transconductance enhanced portions.Type: GrantFiled: March 8, 2004Date of Patent: October 11, 2005Assignee: National Cheng Kung UniversityInventors: Wei-Chou Hsu, Ching-Sung Lee
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Publication number: 20040211955Abstract: An InGaAs/GaAs High Electron Mobility Transistor (HEMT) comprises a buffer layer, a main conducting channel, an InGaAs/GaAs thickness-graded superlattice structure, a mono atom &dgr;-doped carrier supply layer, a Schottky cap layer of gate electrode and an Ohmic cap layer of drain electrode and source electrode which are formed successively on a substrate. The superlattice structure comprises spacer and sub-channel. By using thickness-graded superlattice spacer structure is able to ameliorate lattice-mismatch-induced scattering within heterostucture interfacial, increase range of gate voltage swing in gate electrode, and through real-space transfer generated by bias voltage in high electric field, drain-to-source saturation current proceed step-up phenomenon to forming a HEMT having scalable voltage multi-extrinsic transconductance enhanced portions.Type: ApplicationFiled: March 8, 2004Publication date: October 28, 2004Applicant: NATIONAL CHENG KUNG UNIVERSITYInventors: Wei-Chou Hsu, Ching-Sung Lee
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Publication number: 20020121648Abstract: A double &dgr;-doped In0.34 Al0.66As0.85 Sb0.15/InP heterostructure field-effect transistor has been successfully grown by metalorganic chemical vapor deposition for the first time. Electron mobilities can be enhanced without sacrificing the carrier densities. A turn-on voltage as high as 1 V along with an extremely low gate reverse leakage current of 111 &mgr;A/mm at Vgs=−40V is achieved. The three-terminal on-and off-state breakdown voltages are as high as 40.8V and 16.1V, respectively. The output conductance is as low as 1.8 mS/mm even when the drain-to-source voltage is 15V. The gds is significantly smaller than that of our previously reported InAlAsSb/InGaAs/InP HFET. These characteristics are attributed to the use of the coupled &dgr;-doped structure, InP channel, In0.34 Al0.66As0.85 Sb0.15 Schottky layer, and to the large conduction-band discontinuity (&Dgr;Ec) at the InAlAsSb/InP heterojunction.Type: ApplicationFiled: May 22, 2001Publication date: September 5, 2002Inventors: Wei-Chou Hsu, Yu-Shyan Lin, Chia-Yen Yeh, Yen-Wei Chen
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Patent number: 6429468Abstract: A double &dgr;-doped In0.34 Al0.66As0.85 Sb0.15/InP heterostructure field-effect transistor has been successfully grown by metalorganic chemical vapor deposition for the first time. Electron mobilities can be enhanced without sacrificing the carrier densities. A turn-on voltage as high as 1 V along with an extremely low gate reverse leakage current of 111 &mgr;A/mm at Vgs=−40V is achieved. The three-terminal on-and off-state breakdown voltages are as high as 40.8V and 16.1V,respectively. The output conductance is as low as 1.8 mS/mm even when the drain-to-source voltage is 15V. The gds is significantly smaller than that of our previously reported InAlAsSb/InGaAs/InP HFET. These characteristics are attributed to the use of the coupled &dgr;-doped structure, InP channel, In0.34 Al0.66As0.85 Sb0.15 Schottky layer'and to the large conduction-band discontinuity(&Dgr;Ec) at the InAlAsSb/InP heterojunction.Type: GrantFiled: May 22, 2001Date of Patent: August 6, 2002Assignee: National Science CouncilInventors: Wei-Chou Hsu, Yu-Shyan Lin, Chia-Yen Yeh
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Patent number: 6043518Abstract: Disclosed in this invention is a new four-terminal type and multiple delta-doped transistors with multiple functions grown by low-pressure metalorganic chemical vapor deposition (LP-MOCVD). All the epilayers are grown on n.sup.+ -GaAs substrates. The real-space transfer transistors (RST), the collector is located under the substrate, reveal very strong negative differential resistance phenomena. The RST structure using an InGaAs channel manifests superior characteristics of a very high peak-to-valley current ratio up to 430,000 at room temperature, a peak current as high as 100 mA, very sharp charge injection, and a valley current as broad as 5.5V. Meanwhile, high performance heterostructure field effect transistors can be implemented on the same wafer by further evaporating a gate between source and drain electrodes. In order to significantly reduce leakage current, an ohmic recession is made at the source and drain.Type: GrantFiled: February 11, 1998Date of Patent: March 28, 2000Assignee: National Science CouncilInventors: Wei-Chou Hsu, Chang-Luen Wu
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Patent number: 5777353Abstract: Disclosed in this invention is a new four-terminal type and multiple delta-doped transistors with multiple functions grown by low-pressure metalorganic chemical vapor deposition (LP-MOCVD). All the epilayers are grown on n.sup.+ -GaAs substrates. The real-space transfer transistors (RST), the collector is located under the substrate, reveal very strong negative differential resistance phenomena. The RST structure using an InGaAs channel manifests superior characteristics of a very high peak-to-valley current ratio up to 430,000 at room temperature, a peak current as high as 100 mA, very sharp charge injection, and a valley current as broad as 5.5V. Meanwhile, high performance heterostructure field effect transistors can be implemented on the same wafer by further evaporating a gate between source and drain electrodes. In order to significantly reduce leakage current, an ohmic recession is made at the source and drain.Type: GrantFiled: November 9, 1995Date of Patent: July 7, 1998Assignee: National Science CouncilInventors: Wei-Chou Hsu, Chang-Luen Wu