Patents by Inventor Wei-Chuan Lin

Wei-Chuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210144884
    Abstract: A heat-dissipating component for a mobile device includes a case body, a micro pump, and a heat dissipation tube plate. The case body has a vent hole and a positioning accommodation trough. The bottom of the positioning accommodation trough is in communication with the vent hole. The micro pump is disposed in the positioning accommodation trough and corresponds to the vent hole The heat dissipation tube plate has cooling fluid inside. One end of the heat dissipation tube plate is fixed on the positioning accommodation trough and contacts a heating element of the mobile device. The gas transmitted by the micro pump forms gas flow so as to perform heat exchange with heat absorbed by the heat dissipation tube plate, and the gas flow is discharged out through the vent hole.
    Type: Application
    Filed: October 29, 2020
    Publication date: May 13, 2021
    Inventors: Hao-Jan Mou, Ching-Sung Lin, Chin-Chuan Wu, Chih-Kai Chen, Yung-Lung Han, Chi-Feng Huang, Wei-Ming Lee
  • Patent number: 10999482
    Abstract: An image capturing device includes a circuit board, an image capturing module, a light source module disposed on the circuit board and a connection body disposed above the light source module. The image capturing module has a first lens set and a second lens set disposed on the circuit board. The connection body has a first connection section having a first open end and a second open end. The first open end of the first connection section abuts against the light-emitting component or the upper side of the circuit board in adjacency to the light-emitting component. The first and second open ends together define a first light passage. The light-emitting component is positioned in the first light passage. The image capturing device can effectively avoid light leakage of the image.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: May 4, 2021
    Assignee: Asia Vital Components Co., Ltd.
    Inventors: Wei-Chuan Wang, Ting-Yu Lin, Chin-Liang Yeh
  • Patent number: 8159627
    Abstract: Disclosed is a pixel layout structure capable of increasing the capability of detecting amorphous silicon (a-Si) residue defects and a method for manufacturing the same. Wherein, an a-Si dummy layer is disposed on either one side or both sides of each data line. The design of such an a-Si dummy layer is utilized, so that in an existing testing conditions (by making use of an existing automatic array tester in carrying out the test), in case that there exists an a-Si residue in a pixel, the pixel having defects can be detected through an enhanced capacitance coupling effect and an electron conduction effect. Therefore, through the application of the above-mentioned design, the capability of an automatic array tester can effectively be increased in detecting a defective pixel having a-Si residues.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: April 17, 2012
    Assignee: Century Display (Shenzhen) Co., Ltd
    Inventors: Wei-Chuan Lin, Lung-chuan Chang
  • Publication number: 20110230009
    Abstract: Disclosed is a pixel layout structure capable of increasing the capability of detecting amorphous silicon (a-Si) residue defects and a method for manufacturing the same. Wherein, an a-Si dummy layer is disposed on either one side or both sides of each data line. The design of such an a-Si dummy layer is utilized, so that in an existing testing conditions (by making use of an existing automatic array tester in carrying out the test), in case that there exists an a-Si residue in a pixel, the pixel having defects can be detected through an enhanced capacitance coupling effect and an electron conduction effect. Therefore, through the application of the above-mentioned design, the capability of an automatic array tester can effectively be increased in detecting a defective pixel having a-Si residues.
    Type: Application
    Filed: May 31, 2011
    Publication date: September 22, 2011
    Inventors: Wei-Chuan LIN, Lung-chuan Chang
  • Publication number: 20090267071
    Abstract: Disclosed is a pixel layout structure capable of increasing the capability of detecting amorphous silicon (a-Si) residue defects and a method for manufacturing the same. Wherein, an a-Si dummy layer is disposed on either one side or both sides of each data line. The design of such an a-Si dummy layer is utilized, so that in an existing testing conditions (by making use of an existing automatic array tester in carrying out the test), in case that there exists an a-Si residue in a pixel, the pixel having defects can be detected through an enhanced capacitance coupling effect and an electron conduction effect. Therefore, through the application of the above-mentioned design, the capability of an automatic array tester can effectively be increased in detecting a defective pixel having a-Si residues.
    Type: Application
    Filed: March 17, 2009
    Publication date: October 29, 2009
    Inventors: Wei-Chuan LIN, Lung-chuan Chang
  • Patent number: 7145172
    Abstract: A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: December 5, 2006
    Assignee: Hannstar Display Corporation
    Inventors: Chih-Yu Peng, Wei-Chuan Lin, Chian-Chih Hsiao, Ta-Ko Chuang, Chun-Hung Chu, Chih-Lung Lin, Chin-Mao Lin
  • Patent number: 7087469
    Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming a silicon island and a bottom electrode on the transparent substrate, the silicon island having an undoped region located on the central portion, and two doped regions respectively located on both sides, ii) forming a first silicon nitride layer on the transparent substrate, and iii) forming a stacked layer comprising a second silicon nitride layer and a conductive layer on the undoped region of the silicon island, and the first conductive layer of the stacked layer serving as a gate of a thin film transistor, wherein an etching selectivity ratio of the conductive layer over the dielectric layer is not less than about 5.0.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: August 8, 2006
    Assignee: Hannstar Display Corp.
    Inventors: Chih-Yu Peng, Wei-Chuan Lin, Chian-Chih Hsiao, Ta-Ko Chuang, Chun-Hung Chu, Chih-Lung Lin, Chin-Mao Lin
  • Patent number: 6953715
    Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming an undoped amorphous silicon layer on a silicon nitride layer, ii) forming an etching mask on the undoped amorphous silicon layer, and iii) forming two doped amorphous silicon layers on portion of the undoped amorphous silicon layer and the etching mask, the two doped amorphous silicon layers being spaced apart and located on either side of the gate, wherein an etching selectivity ratio of the undpoed and doped amorphous silicon layers over the dielectric layer being not less than about 5.0.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: October 11, 2005
    Assignee: HannStar Display Corporation
    Inventors: Chih-Yu Peng, Wei-Chuan Lin, Chian-Chih Hsiao, Ta-Ko Chuang, Chun-Hung Chu, Chih-Lung Lin, Chin-Mao Lin
  • Publication number: 20050082492
    Abstract: An X-ray image detector with a tandem-gate TFT. A storage capacitor comprises a bottom conductive layer connected to a ground line, and a top conductive layer insulated from the bottom conductive layer by an insulating layer. A thin film transistor controls release of the electric charge stored in the storage capacitor, wherein the thin film transistor comprises two electrically connected in series channel regions.
    Type: Application
    Filed: October 14, 2004
    Publication date: April 21, 2005
    Inventors: Wei-Chuan Lin, Kei-Hsiung Yang
  • Publication number: 20050037533
    Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming an undoped amorphous silicon layer on a silicon nitride layer, ii) forming an etching mask on the undoped amorphous silicon layer, and iii) forming two doped amorphous silicon layers on portion of the undoped amorphous silicon layer and the etching mask, the two doped amorphous silicon layers being spaced apart and located on either side of the gate, wherein an etching selectivity ratio of the undpoed and doped amorphous silicon layers over the dielectric layer being not less than about 5.0.
    Type: Application
    Filed: September 3, 2004
    Publication date: February 17, 2005
    Inventors: Chih-Yu Peng, Wei-Chuan Lin, Chian-Chih Hsiao, Ta-Ko Chuang, Chun-Hung Chu, Chih-Lung Lin, Chin-Mao Lin
  • Publication number: 20050032263
    Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming a silicon island and a bottom electrode on the transparent substrate, the silicon island having an undoped region located on the central portion, and two doped regions respectively located on both sides, ii) forming a first silicon nitride layer on the transparent substrate, and iii) forming a stacked layer comprising a second silicon nitride layer and a conductive layer on the undoped region of the silicon island, and the first conductive layer of the stacked layer serving as a gate of a thin film transistor, wherein an etching selectivity ratio of the conductive layer over the dielectric layer is not less than about 5.0.
    Type: Application
    Filed: September 3, 2004
    Publication date: February 10, 2005
    Inventors: Chih-Yu Peng, Wei-Chuan Lin, Chian-Chih Hsiao, Ta-Ko Chuang, Chun-Hung Chu, Chih-Lung Lin, Chin-Mao Lin
  • Publication number: 20050023533
    Abstract: A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.
    Type: Application
    Filed: September 2, 2004
    Publication date: February 3, 2005
    Inventors: Chih-Yu Peng, Wei-Chuan Lin, Chian-Chih Hsiao, Ta-Ko Chuang, Chun-Hung Chu, Chih-Lung Lin, Chin-Mao Lin
  • Patent number: 6800510
    Abstract: A method of controlling the capacitance of the TFT-LCD storage capacitor is provided. The gate dielectric layer of the TFT is composed of a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when a doped and an undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled; thereby the capacitance of the storage capacitor can be controlled.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: October 5, 2004
    Assignee: HannStar Display Corporation
    Inventors: Chih-Yu Peng, Wei-Chuan Lin, Chian-Chih Hsiao, Ta-Ko Chuang, Chun-Hung Chu, Chih-Lung Lin, Chin-Mao Lin
  • Publication number: 20040084678
    Abstract: A method of controlling the capacitance of the TFT-LCD storage capacitor is provided. The gate dielectric layer of the TFT is composed of a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when a doped and an undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled; thereby the capacitance of the storage capacitor can be controlled.
    Type: Application
    Filed: November 6, 2002
    Publication date: May 6, 2004
    Inventors: Chih-Yu Peng, Wei-Chuan Lin, Chian-Chih Hsiao, Ta-Ko Chuang, Chun-Hung Chu, Chih-Lung Lin, Chin-Mao Lin