Patents by Inventor Wei-Chuan Tsai
Wei-Chuan Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20190057895Abstract: A manufacturing method of an interconnect structure including the following steps is provided. A dielectric layer is formed on a silicon layer, wherein an opening exposing the silicon layer is in the dielectric layer. A metal layer is formed on the surface of the opening. A stress adjustment layer is formed on the metal layer. A thermal process is performed to react the metal layer with the silicon layer to form a metal silicide layer on the silicon layer. The stress adjustment layer is removed after the thermal process is performed. A barrier layer is formed on the surface of the opening.Type: ApplicationFiled: September 21, 2017Publication date: February 21, 2019Applicant: United Microelectronics Corp.Inventors: Li-Han Chen, Chun-Chieh Chiu, Wei-Chuan Tsai, Yen-Tsai Yi
-
Patent number: 10199269Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.Type: GrantFiled: November 28, 2016Date of Patent: February 5, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Han Chen, Yen-Tsai Yi, Chun-Chieh Chiu, Min-Chuan Tsai, Wei-Chuan Tsai, Hsin-Fu Huang
-
Patent number: 10192826Abstract: A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.Type: GrantFiled: December 26, 2017Date of Patent: January 29, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kun-Ju Li, Kuo-Chin Hung, Min-Chuan Tsai, Wei-Chuan Tsai, Yi-Han Liao, Chun-Tsen Lu, Fu-Shou Tsai, Li-Chieh Hsu
-
Publication number: 20180366368Abstract: The present invention provides a method for forming a contact structure, the method includes proving a substrate. An oxygen-containing dielectric layer is formed on the substrate. Next, a non-oxygen layer is formed on the oxygen-containing dielectric layer and a contact hole is then formed in the oxygen-containing dielectric layer. A metal layer is then formed in the contact hole and on the non-oxygen layer, with the non-oxygen layer disposed between the oxygen-containing dielectric layer and the metal layer. An anneal process is then performed to the metal layer, and a conductive layer is filled in the contact hole.Type: ApplicationFiled: June 18, 2017Publication date: December 20, 2018Inventors: Chun-Chieh Chiu, Wei-Chuan Tsai, Yen-Tsai Yi, Li-Han Chen
-
Patent number: 10134629Abstract: A method for manufacturing a semiconductor structure includes the following steps. At first, a titanium layer is formed on a preformed layer. Then, a first titanium nitride layer is formed on the titanium layer. A first plasma treatment is applied to the first titanium nitride layer such that the first titanium nitride layer has a first N/Ti ratio. A second titanium nitride layer is formed on the first titanium nitride layer. A second plasma treatment is applied to the second titanium nitride layer such that the second titanium nitride layer has a second N/Ti ratio larger than the first N/Ti ratio.Type: GrantFiled: September 6, 2017Date of Patent: November 20, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Wen Hung, Yen-Tsai Yi, Wei-Chuan Tsai, En-Chiuan Liou, Chih-Wei Yang
-
Publication number: 20180151428Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.Type: ApplicationFiled: November 28, 2016Publication date: May 31, 2018Inventors: Li-Han Chen, Yen-Tsai Yi, Chun-Chieh Chiu, Min-Chuan Tsai, Wei-Chuan Tsai, Hsin-Fu Huang
-
Patent number: 9985110Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.Type: GrantFiled: July 21, 2017Date of Patent: May 29, 2018Assignee: United Microelectronics Corp.Inventors: Pin-Hong Chen, Kuo-Chih Lai, Chia-Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Min-Chuan Tsai, Kuo-Chin Hung, Wei-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu
-
Publication number: 20180138125Abstract: A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.Type: ApplicationFiled: December 26, 2017Publication date: May 17, 2018Inventors: Kun-Ju Li, Kuo-Chin Hung, Min-Chuan Tsai, Wei-Chuan Tsai, Yi-Han Liao, Chun-Tsen Lu, Fu-Shou Tsai, Li-Chieh Hsu
-
Patent number: 9887158Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, a first trench formed in the first dielectric layer, a first barrier layer formed in the first trench, a first nucleation layer formed on the first barrier layer, a first metal layer formed on the first nucleation layer, and a first high resistive layer sandwiched in between the first barrier layer and the first metal layer.Type: GrantFiled: November 2, 2016Date of Patent: February 6, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kun-Ju Li, Kuo-Chin Hung, Min-Chuan Tsai, Wei-Chuan Tsai, Yi-Han Liao, Chun-Tsen Lu, Fu-Shou Tsai, Li-Chieh Hsu
-
Patent number: 9853123Abstract: A semiconductor structure includes a substrate having thereon a dielectric layer. An opening is formed in the dielectric layer. The opening includes a bottom surface and a sidewall surface. A diffusion barrier layer is conformally disposed along the sidewall surface and the bottom surface of the opening. A nucleation metal layer is conformally disposed on the diffusion barrier layer. A bulk metal layer is disposed on the nucleation metal layer. A film-growth retarding layer is disposed between the nucleation metal layer and the bulk metal layer.Type: GrantFiled: October 28, 2015Date of Patent: December 26, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Chin Hung, Wei-Chuan Tsai, Kuan-Chun Lin
-
Publication number: 20170323950Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.Type: ApplicationFiled: July 21, 2017Publication date: November 9, 2017Applicant: United Microelectronics Corp.Inventors: Pin-Hong Chen, Kuo-Chih Lai, Chia-Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Min-Chuan Tsai, Kuo-Chin Hung, Wei-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu
-
Patent number: 9755047Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.Type: GrantFiled: October 27, 2015Date of Patent: September 5, 2017Assignee: United Microelectronics Corp.Inventors: Pin-Hong Chen, Kuo-Chih Lai, Chia-Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Min-Chuan Tsai, Kuo-Chin Hung, Wei-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu
-
Patent number: 9735015Abstract: A method of manufacturing a semiconductor structure, comprising: providing a preliminary structure having a first region and a second region and comprising a plurality of first trenches in the first region; forming a metal layer filling the first trenches covering on the preliminary structure, wherein the metal layer comprises a concave portion in the second region and the concave portion defines an opening; forming a metal nitride layer on the metal layer by an nitride treatment; and performing a planarization process to remove the metal nitride layer and a portion of the metal layer to expose the preliminary structure.Type: GrantFiled: December 5, 2016Date of Patent: August 15, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Kun Ju Li, Hsin Jung Liu, Wei-Chuan Tsai, Min-Chuan Tsai, Yi Han Liao, Chun-Tsen Lu, Chun-Lin Chen, Jui-Ming Yang, Kuo-Chin Hung
-
Publication number: 20170125548Abstract: A semiconductor structure includes a substrate having thereon a dielectric layer. An opening is formed in the dielectric layer. The opening includes a bottom surface and a sidewall surface. A diffusion barrier layer is conformally disposed along the sidewall surface and the bottom surface of the opening. A nucleation metal layer is conformally disposed on the diffusion barrier layer. A bulk metal layer is disposed on the nucleation metal layer. A film-growth retarding layer is disposed between the nucleation metal layer and the bulk metal layer.Type: ApplicationFiled: October 28, 2015Publication date: May 4, 2017Inventors: Kuo-Chin Hung, Wei-Chuan Tsai, Kuan-Chun Lin
-
Patent number: 9640482Abstract: The present invention utilizes a barrier layer in the contact hole to react with an S/D region to form a silicide layer. After forming the silicide layer, a directional deposition process is performed to form a first metal layer primarily on the barrier layer at the bottom of the contact hole, so that very little or even no first metal layer is disposed on the barrier layer at the sidewall of the contact hole. Then, the second metal layer is deposited from bottom to top in the contact hole as the deposition rate of the second metal layer on the barrier layer is slower than the deposition rate of the second metal layer on the first metal layer.Type: GrantFiled: April 13, 2016Date of Patent: May 2, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Pin-Hong Chen, Kuo-Chih Lai, Min-Chuan Tsai, Chun-Chieh Chiu, Li-Han Chen, Yen-Tsai Yi, Wei-Chuan Tsai, Kuo-Chin Hung, Hsin-Fu Huang, Chi-Mao Hsu
-
Publication number: 20170117379Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.Type: ApplicationFiled: October 27, 2015Publication date: April 27, 2017Inventors: Pin-Hong Chen, Kuo-Chih Lai, Chia-Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Min-Chuan Tsai, Kuo-Chin Hung, Wei-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu
-
Patent number: 8053474Abstract: The present invention discloses compounds with a carboxyl acid group and an amide group which also containing the tertiary amino groups. The carboxyl acid group having a partial negative charge can attract the tertiary amino group with each other to form a quaternary ammonium salt structure, so that the compounds are easy to dissolve in water. Moreover, these compounds having a mushroom tyrosinase-inhibition effect and have the potential to use in the cosmetics for skin whitening.Type: GrantFiled: December 29, 2009Date of Patent: November 8, 2011Assignee: Corum Inc.Inventors: Wei-Chuan Tsai, Chen-Yin Chen, Ming-Yi Chiu, Yi-Fan Ling, Nai-Hsuan Hsu
-
Publication number: 20110065954Abstract: The present invention discloses compounds with a carboxyl acid group and an amide group which also containing the tertiary amino groups. The carboxyl acid group having a partial negative charge can attract the tertiary amino group with each other to form a quaternary ammonium salt structure, so that the compounds are easy to dissolve in water. Moreover, these compounds having a mushroom tyrosinase-inhibition effect and have the potential to use in the cosmetics for skin whitening.Type: ApplicationFiled: December 29, 2009Publication date: March 17, 2011Applicant: CORUM INC.Inventors: Wei-Chuan Tsai, Chen-Yin Chen, Ming-Yi Chiu, Yi-Fan Ling, Nai-Hsuan Hsu
-
Patent number: 7741496Abstract: The present invention discloses the ascorbic acid derivatives. The inventive molecules that combine with one or two hydrophilic headgroups connected by a hydrophobic spacer can increase skin penetration.Type: GrantFiled: September 3, 2009Date of Patent: June 22, 2010Assignee: Corum Inc.Inventors: Wei-Chuan Tsai, Chen-Yin Chen, Ming-Yi Chiu, Yi-Fan Ling, Nai-Hsuan Hsu
-
Publication number: 20100056809Abstract: The present invention discloses the ascorbic acid derivatives. The inventive molecules that combine with one or two hydrophilic headgroups connected by a hydrophobic spacer can increase skin penetration.Type: ApplicationFiled: September 3, 2009Publication date: March 4, 2010Applicant: CORUM INC.Inventors: Wei-Chuan Tsai, Chen-Yin Chen, Ming-Yi Chiu, Yi-Fan Ling, Nai-Hsuan Hsu