Abstract: A method with a SOTIF scene collection and a self-update mechanism, which is applied to a vehicle, includes a situation judging step, a scene collecting step, a modifying step, a verifying step, and an updating step. As the situation judging step judges that the sensing control dataset belongs to the accident scene dataset, the sensing control dataset collected by the scene collecting step belongs to a SOTIF scene.

Abstract: In a projection device and a light source system thereof, the light source system includes a light source module, a driver, and a control circuit. The light source module includes light sources to provide beams with different wavelength ranges. According to a selection signal, the control circuit selects one of a first pulse width modulation signal, a second pulse width modulation signal, and a third pulse width modulation signal as a pulse width modulation signal to output to the driver. The driver drives the light source corresponding to the selection signal with the pulse width modulation signal provided by the control circuit.

Abstract: A hairpin stator includes a core, slot-positions and hairpin wires. The core includes a first side and a second side. The slot-positions are configured on the core circumferentially to form M radially-adjacent slot-position layers, wherein M is an odd number greater than or equal to 5. The hairpin wires are configured in the slot-positions and connected to form a plurality of windings. The hairpin wires include a plurality of first U-shaped wires arranged at an outermost slot-position layer in the radial direction and a plurality of second U-shaped wires arranged at an innermost slot-position layer in the radial direction. Each first U-shaped wire includes a U-shaped section arranged at the outermost slot-position layer and protruding from the first side of the core. Each second U-shaped wire includes a U-shaped section arranged at the innermost slot-position layer and protruding from the second side of the core.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes a step of performing a chemical mechanical polishing process on a first silicon oxide layer to form a planar surface layer; surface treatment is performed on the planar surface layer to form a treated planarization layer, and a second silicon oxide layer is formed on the treated planarization layer.

Abstract: A backlight module has a back plate having a supporting surface, a reflective sheet, a light board, and at least one connecting structure. The reflective sheet is arranged on the supporting surface of the back plate along an assembling direction. The light board is disposed between the reflective sheet and the back plate. The at least one connecting structure has a recess and a post. The recess has an opening and a guiding surface connected to the opening and inclined along a guiding direction relative to the supporting surface. The post has an end portion configured to pass through the opening of the recess and hook the guiding surface. The back plate and the reflective sheet are mounted via the recess and the post. A display device is also provided.

Abstract: An indoor occupancy distribution analysis system is provided, which includes a base station and a network management device that communicate with each other. The base station is configured to collect performance indicators corresponding to each user equipment from the base station. The performance indicators are associated with the communication between the user equipment and the base station. The network management device is configured to receive these performance indicators, input them into a classifier, obtain the inference result output by the classifier, and derive occupancy distribution from the inference result.

Abstract: Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.

Abstract: A method for secure data transmission is provided. The method includes requesting a key from an encryption and decryption application in a near real-time radio access network (RAN) intelligent controller (Near-RT RIC). The method includes receiving the key from the encryption and decryption application. The method includes encrypting data by using the key, and generating encrypted data. The method includes storing the encrypted data to a database in the Near-RT RIC through a shared data layer.

Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.

Abstract: An electronic package and a manufacturing method thereof are provided, in which an offset suppression layer is formed on a carrier, a first electronic element and a second electronic element are respectively disposed on the offset suppression layer, and an encapsulant is formed on the offset suppression layer to respectively cover the first electronic element and the second electronic element. The offset suppression layer effectively suppresses or prevents possible offset caused by the encapsulant to the first electronic element and the second electronic element, thereby avoiding yield loss of the semiconductor package.

Abstract: A phase-change temperature regulating system and an electronic device testing apparatus and method are described. In an embodiment, the system uses a temperature regulating fluid chamber containing a temperature regulating fluid to allow the temperature regulating fluid to cover at least a part of at least one surface of an electronic component. When a temperature of the electronic component reaches a boiling point of the temperature regulating fluid, the temperature regulating fluid becomes steam through a phase change to transfer heat energy outward from the electronic component, and condenses on an inner surface of the fluid chamber to further transfer heat energy of the steam to a temperature-regulating apparatus. The condensed temperature regulating fluid flows back to the temperature regulating fluid, thereby continuously circulating.

Abstract: A base is configured for a bracket. The base includes a hollow body, a plurality of supporting branches, and an illuminating module. The hollow body is connected to the bracket and has a bottom part and a first sidewall. The bottom part has an open hole. The first sidewall has a transparent structure. The plurality of supporting branches is disposed around the hollow body to lift the hollow body. The illuminating module is disposed in the hollow body and includes a sleeve and a base plate. The sleeve has a second sidewall, a first end, and a second end opposite to the first end. The second sidewall has an opening. The position of the opening is corresponding to the transparent structure. The base plate is disposed on the first end. The base plate is provided with a light source. The light source projects light beams toward the second end.

Abstract: A hairpin stator includes an iron core, a plurality of slot-positions and a plurality of hairpin wires. The slot-positions are located in the circumferential direction of the iron core, and form a plurality of adjacent slot-position layers in the radial direction. The iron core includes polar regions, each polar region includes phases, and each phase includes phase slots. The hairpin wires are arranged in the slot-positions of the phase slots of the same phases of the polar regions, and the hairpin wires are connected to form windings. The hairpin wires include transpolar hairpin wires. A span of the transpolar hairpin wires on an insertion side of the iron core is equal to a quotient, which is obtained by dividing a total number of the phase slots by a total number of the polar regions, plus 1 or minus 1.

Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.

Abstract: Systems and methods are provided for predicting irregular motions of one or more mechanical components of a semiconductor processing apparatus. A mechanical motion irregular prediction system includes one or more motion sensors that sense motion-related parameters associated with at least one mechanical component of a semiconductor processing apparatus. The one or more motion sensors output sensing signals based on the sensed motion-related parameters. Defect prediction circuitry predicts an irregular motion of the at least one mechanical component based on the sensing signals.

Abstract: A semiconductor structure includes a semiconductor substrate, an interconnection structure, a color filter, and a first isolation structure. The semiconductor substrate includes a first surface and a second surface opposite to the first surface. The interconnection structure is disposed over the first surface, and the color filter is disposed over the second surface. The first isolation structure includes a bottom portion, an upper portion and a diffusion barrier layer surrounding a sidewall of the upper portion. A top surface of the upper portion of the first isolation structure extends into and is in contact with a dielectric layer of the interconnection structure.

Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.

Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.

Abstract: In some embodiments, the present disclosure relates to an image sensor integrated chip. The image sensor integrated chip includes a floating diffusion node disposed within a substrate. A plurality of photodetectors are disposed around the floating diffusion node, as viewed in a plan-view, and a plurality of transfer transistor gates are disposed between the floating diffusion node and the plurality of photodetectors, as viewed in the plan-view. One or more transistor gates are disposed on the substrate. A device isolation structure extends in a closed loop around the one or more transistor gates. The device isolation structure is laterally offset from the floating diffusion node.

Abstract: A method for routing of redistribution layers in IC package is proposed, which is executed by a computer, the method comprising using the computer to perform the following: providing design rules, a set of I/O pads and bump pads and a pre-assignment netlist; performing a global routing which generates the guides for any non-acute angle RDL routing; and performing a detailed routing which adjusts the access point for shorter wirelength and finishes the routing. After the access points are located, the nets tile by tile are routed.