Patents by Inventor Wei-Chun CHOU

Wei-Chun CHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10629726
    Abstract: The present disclosure provides a high-voltage semiconductor device, including: a substrate; an epitaxial layer disposed over the substrate and having a first conductive type; a gate structure disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate structure respectively; and a stack structure disposed between the gate structure and the drain region, wherein the stack structure includes: a blocking layer; an insulating layer disposed over the blocking layer; and a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure. The present disclosure also provides a method for manufacturing the high-voltage semiconductor device.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 21, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chung-Ren Lao, Hsing-Chao Liu, Chu-Feng Chen, Wei-Chun Chou
  • Patent number: 9831305
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer; a first conductive type first well region disposed in the substrate and the epitaxial layer; a second conductive type first buried layer and a second conductive type second buried layer disposed at opposite sides of the first conductive type first well region, respectively; a first conductive type second well region disposed in the epitaxial layer and being in direct contact with the first conductive type first well region; a second conductive type third buried layer disposed in the first conductive type first well region and/or the first conductive type second well region; a second conductive type doped region disposed in the first conductive type second well region; a gate structure; a drain contact plug; and a source contact plug.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: November 28, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chu-Feng Chen, Wei-Chun Chou, Chien-Wei Chiu
  • Publication number: 20170323938
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer; a first conductive type first well region disposed in the substrate and the epitaxial layer; a second conductive type first buried layer and a second conductive type second buried layer disposed at opposite sides of the first conductive type first well region, respectively; a first conductive type second well region disposed in the epitaxial layer and being in direct contact with the first conductive type first well region; a second conductive type third buried layer disposed in the first conductive type first well region and/or the first conductive type second well region; a second conductive type doped region disposed in the first conductive type second well region; a gate structure; a drain contact plug; and a source contact plug.
    Type: Application
    Filed: May 6, 2016
    Publication date: November 9, 2017
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chu-Feng CHEN, Wei-Chun CHOU, Chien-Wei CHIU
  • Publication number: 20160172490
    Abstract: The present disclosure provides a high-voltage semiconductor device, including: a substrate; an epitaxial layer disposed over the substrate and having a first conductive type; a gate structure disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate structure respectively; and a stack structure disposed between the gate structure and the drain region, wherein the stack structure includes: a blocking layer; an insulating layer disposed over the blocking layer; and a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure. The present disclosure also provides a method for manufacturing the high-voltage semiconductor device.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 16, 2016
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chung-Ren LAO, Hsing-Chao LIU, Chu-Feng CHEN, Wei-Chun CHOU
  • Patent number: 9343572
    Abstract: A high-voltage semiconductor device is provided. The high-voltage semiconductor device includes a substrate; an epitaxial layer and a gate structure; a first conductive type first high-voltage well region and a second conductive type high-voltage well region disposed in the epitaxial layer at opposite sides of the gate structure respectively, wherein the first conductive type is different from the second conductive type; a source region and a drain region; and a stack structure disposed between the gate structure and the drain region, wherein the stack structure includes: a blocking layer; an insulating layer disposed over the blocking layer; and a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure. A method for manufacturing the high-voltage semiconductor device is also provided.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: May 17, 2016
    Assignee: Vangaurd International Semiconductor Corporation
    Inventors: Chung-Ren Lao, Hsing-Chao Liu, Chu-Feng Chen, Wei-Chun Chou
  • Patent number: 9224862
    Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: December 29, 2015
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wei-Chun Chou, Yi-Hung Chiu, Chu-Feng Chen, Cheng-Yi Hsieh, Chung-Ren Lao
  • Publication number: 20150054071
    Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.
    Type: Application
    Filed: August 26, 2014
    Publication date: February 26, 2015
    Inventors: Wei-Chun CHOU, Yi-Hung CHIU, Chu-Feng CHEN, Cheng-Yi HSIEH, Chung-Ren LAO
  • Patent number: 8847332
    Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: September 30, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wei-Chun Chou, Yi-Hung Chiu, Chu-Feng Chen, Cheng-Yi Hsieh, Chung-Ren Lao
  • Publication number: 20120267715
    Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.
    Type: Application
    Filed: April 20, 2011
    Publication date: October 25, 2012
    Inventors: Wei-Chun CHOU, Yi-Hung CHIU, Chu-Feng CHEN, Cheng-Yi HSIEH, Chung-Ren LAO