Patents by Inventor Wei-Chun CHOU

Wei-Chun CHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210024267
    Abstract: A packaging structure is used for carrying at least one carried object. The packaging structure comprises a carrying unit and a covering member. The carrying unit includes a supporting plate, at least one first side plate connected to the edge of the supporting plate, and at least one combing member. The supporting plate has two opposite surfaces, and the first side plate is able to bend to one of the surfaces of the supporting plate, so that the carrying unit is able to present as an unfolded state or a folded state. The first side plate is stacked on the supporting plate when the carrying unit is in the folded state, and the combing member keeps the first side plate stacked on the supporting plate. The covering member is used for positioning the carried object on the carrying unit. The invention also provides a delivering device for clamping and positioning a plurality of the aforementioned packaging structures in an upright manner.
    Type: Application
    Filed: July 20, 2020
    Publication date: January 28, 2021
    Inventors: Fang-Chun LIU, Hung-Lin CHOU, Chao-Hsu CHEN, Wei-Ju CHEN, Shu-Juan SONG, Ren-Zhu CAO, Tian-Yu ZHAO, Chih-Ming CHAN
  • Patent number: 10879120
    Abstract: A self aligned via and a method for fabricated a semiconductor device using a double-trench constrained self alignment process to form the via. The method includes forming a first trench and depositing a first metal into the first trench. Afterwards, the process includes depositing a dielectric layer over the first metal such that a top surface of the dielectric layer is at substantially the same level as the top surface of the first trench. Next, a second trench is formed and a via is formed by etching the portion of the dielectric layer exposed by the overlapping region between the first trench and the second trench. The via exposes a portion of the first metal and a second metal is deposited into the second trench such that the second metal is electrically coupled to the first metal.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: December 29, 2020
    Assignees: Taiwan Semiconductor Manufacturing, Company Limited
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou
  • Publication number: 20200387686
    Abstract: Optical sensors and their making methods are described herein. In some embodiments, a described sensing apparatus includes: an image sensor; a collimator above the image sensor, wherein the collimator includes an array of apertures; and an optical filtering layer above the collimator, wherein the optical filtering layer is configured to filter a portion of light to be transmitted into the array of apertures.
    Type: Application
    Filed: May 7, 2020
    Publication date: December 10, 2020
    Inventors: You-Cheng JHANG, Han-Zong PAN, Wei-Ding WU, Jiu-Chun WENG, Hsin-Yu CHEN, Chen-San CHOU, Chin-Min LIN
  • Publication number: 20200303551
    Abstract: A method for forming a non-planar semiconductor device includes: forming a fin structure protruding from a front side of a substrate of the non-planar semiconductor device; depositing a dielectric region on the front side of the substrate, the dielectric region including a conductive rail buried within the dielectric region and in parallel with the fin structure; etching the dielectric region to create a first opening in the dielectric region to expose the conductive rail; depositing a plurality of conductive regions on the dielectric region, one of the conductive regions contacting the conductive rail through the first opening; etching the substrate from a backside of the substrate to form a second opening to expose the conductive rail; and filling a first conductive material into the second opening to form a through-substrate via in the substrate.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Inventors: CHIH-LIANG CHEN, LEI-CHUN CHOU, JACK LIU, KAM-TOU SIO, HUI-TING YANG, WEI-CHENG LIN, CHUN-HUNG LIOU, JIANN-TYNG TZENG, CHEW-YUEN YOUNG
  • Patent number: 10700207
    Abstract: A semiconductor device includes a substrate, a dielectric region, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The plurality of conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and is electrically connected to a first conductive region of the plurality of conductive regions. The conductive structure is arranged to penetrate through the substrate and formed under the first conductive rail. The conductive structure is electrically connected to the first conductive rail.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Liang Chen, Lei-Chun Chou, Jack Liu, Kam-Tou Sio, Hui-Ting Yang, Wei-Cheng Lin, Chun-Hung Liou, Jiann-Tyng Tzeng, Chew-Yuen Young
  • Publication number: 20200153859
    Abstract: Preventing Transport Layer Security session man-in-the-middle attacks is provided. A first security digest generated by an endpoint device is compared with a second security digest received from a peer device. It is determined whether a match exists between the first security digest and the second security digest based on the comparison. In response to determining that a match does not exist between the first security digest and the second security digest, a man-in-the-middle attack is detected and a network connection for a Transport Layer Security session is terminated with the peer device.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 14, 2020
    Inventors: Wei-Hsiang Hsiung, Sheng-Tung Hsu, Kuo-Chun Chen, Chih-Hung Chou
  • Publication number: 20200126824
    Abstract: A super thin heating disk includes an upper cover made of metal, the upper cover being formed with a receiving groove; a lower cover made of metal and installed within the receiving groove; the heating coil being distributed in the receiving groove; a heating coil installed within the receiving groove, two ends of the heating coil being installed with two electrodes, respectively, which are connected to external positive and negative electrodes for current conduction; a thermal couple installed in the receiving groove for detecting temperatures of the heating coil; the thermal couple being connected to two connection wires for conducting external transmission lines so that detection temperature data can be transferred out; and two insulation layers installed in the receiving groove and at an upper and a lower side of the heating coil.
    Type: Application
    Filed: October 17, 2018
    Publication date: April 23, 2020
    Inventors: Kuo Yang Ma, Mu-Chun Ho, Wei-Chuan Chou, Pei-Shan Li, Yi Hsiang Chen, Cheng Feng Li
  • Patent number: 10629726
    Abstract: The present disclosure provides a high-voltage semiconductor device, including: a substrate; an epitaxial layer disposed over the substrate and having a first conductive type; a gate structure disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate structure respectively; and a stack structure disposed between the gate structure and the drain region, wherein the stack structure includes: a blocking layer; an insulating layer disposed over the blocking layer; and a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure. The present disclosure also provides a method for manufacturing the high-voltage semiconductor device.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 21, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chung-Ren Lao, Hsing-Chao Liu, Chu-Feng Chen, Wei-Chun Chou
  • Patent number: 10587634
    Abstract: A system, method and computer program product for detecting distributed denial-of-service (DDoS) attacks is provided. Current aggregated flow information for a defined period of time is analyzed. It is determined whether network flow increased above a defined flow threshold value to a second data processing system connected to a network within the defined period of time based on analyzing the current aggregated flow information. In response to determining that the network flow has increased above the defined flow threshold value to the second data processing system connected to the network within the defined period of time, it is determined that the second data processing system is under a DDoS attack.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kuo-Chun Chen, Chih-Hung Chou, Wei-Hsiang Hsiung, Sheng-Tung Hsu
  • Publication number: 20200043741
    Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.
    Type: Application
    Filed: October 14, 2019
    Publication date: February 6, 2020
    Inventors: Lei-Chun Chou, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Hsin-Chih Chen, Shi Ning Ju, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Cheng Lin, Wei-Liang Lin
  • Publication number: 20200006514
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.
    Type: Application
    Filed: September 4, 2019
    Publication date: January 2, 2020
    Inventors: Kuo-Chih Lai, Yun-Tzu Chang, Wei-Ming Hsiao, Nien-Ting Ho, Shih-Min Chou, Yang-Ju Lu, Ching-Yun Chang, Yen-Chen Chen, Kuan-Chun Lin, Chi-Mao Hsu
  • Patent number: 10491625
    Abstract: A system and computer program product for preventing abnormal application activity is provided. Packets are retrieved from a packet buffer using packet location information corresponding to information associated with the abnormal application activity in a data processing system. The packets are analyzed to identify content of the network packets causing the abnormal application activity. Network packets containing the content causing the abnormal application activity in the data processing system are blocked.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: November 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kuo-Chun Chen, Chih-Hung Chou, Wei-Hsiang Hsiung, Sheng-Tung Hsu
  • Patent number: 10490643
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: November 26, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Yun-Tzu Chang, Wei-Ming Hsiao, Nien-Ting Ho, Shih-Min Chou, Yang-Ju Lu, Ching-Yun Chang, Yen-Chen Chen, Kuan-Chun Lin, Chi-Mao Hsu
  • Patent number: 10484420
    Abstract: A method for preventing abnormal application activity is provided. Packets are retrieved from a packet buffer using packet location information corresponding to information associated with the abnormal application activity in a data processing system. The packets are analyzed to identify content of the network packets causing the abnormal application activity. Network packets containing the content causing the abnormal application activity in the data processing system are blocked.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kuo-Chun Chen, Chih-Hung Chou, Wei-Hsiang Hsiung, Sheng-Tung Hsu
  • Patent number: 10446406
    Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: October 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Lei-Chun Chou, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Hsin-Chih Chen, Shi Ning Ju, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Cheng Lin, Wei-Liang Lin
  • Publication number: 20190279887
    Abstract: A vapor reduction device for a semiconductor wafer has a plurality of heat plates which are spaced arranged longitudinally for receiving a plurality of wafers, the heat plates are integrated into a heating frame which is further placed into a casing. The movements of the heat plates within the casing causes that the wafers can be heated rapidly and uniformly so as to evaporated vapor effectively. The heat plates are separable from the heating frame and thus a number of the heat plates is selectable as desired. The heating temperature for the heat plates is controllable independently so that the temperatures of the wafers are controllable so that the temperature differences of the wafers are controllable to be uniformly distributed.
    Type: Application
    Filed: March 7, 2018
    Publication date: September 12, 2019
    Inventors: Kuo Yang Ma, Zhi Kai Huang, Mu-Chun Ho, Wei Chuan Chou, Chun-Fu Wang, Yi-Hsiang Chen, Ying Hsien Cheng
  • Publication number: 20190244787
    Abstract: A plasma etching reaction chamber includes a casing having a receiving chamber; a base liftably installed below the receiving chamber; a first electrode and a second electrode; and a radio frequency electrode rod. The second electrode has a plurality of water channels and a bottom of the second electrode is installed with two cooling water tubes which are communicated with the plurality of water channels; upper sides of the two cooling water tubes are hidden within the driving rod and lower sides thereof extend downwards to be out of the casing so that external cooling water can flow into the cooling water tubes and then to the water channels to achieve the object of cooling.
    Type: Application
    Filed: February 2, 2018
    Publication date: August 8, 2019
    Inventors: Wei-Chuan Chou, Zhi Kai Huang, Mu-Chun Ho, Chun-Fu Wang, Yi-Hsiang Chen, Hsin-Chih Chiu, Yao-Syuan Cheng
  • Publication number: 20190164882
    Abstract: A semiconductor device includes a substrate, a dielectric region, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The plurality of conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and is electrically connected to a first conductive region of the plurality of conductive regions. The conductive structure is arranged to penetrate through the substrate and formed under the first conductive rail. The conductive structure is electrically connected to the first conductive rail.
    Type: Application
    Filed: May 30, 2018
    Publication date: May 30, 2019
    Inventors: CHIH-LIANG CHEN, LEI-CHUN CHOU, JACK LIU, KAM-TOU SIO, HUI-TING YANG, WEI-CHENG LIN, CHUN-HUNG LIOU, JIANN-TYNG TZENG, CHEW-YUEN YOUNG
  • Patent number: 9831305
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer; a first conductive type first well region disposed in the substrate and the epitaxial layer; a second conductive type first buried layer and a second conductive type second buried layer disposed at opposite sides of the first conductive type first well region, respectively; a first conductive type second well region disposed in the epitaxial layer and being in direct contact with the first conductive type first well region; a second conductive type third buried layer disposed in the first conductive type first well region and/or the first conductive type second well region; a second conductive type doped region disposed in the first conductive type second well region; a gate structure; a drain contact plug; and a source contact plug.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: November 28, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chu-Feng Chen, Wei-Chun Chou, Chien-Wei Chiu
  • Publication number: 20170323938
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer; a first conductive type first well region disposed in the substrate and the epitaxial layer; a second conductive type first buried layer and a second conductive type second buried layer disposed at opposite sides of the first conductive type first well region, respectively; a first conductive type second well region disposed in the epitaxial layer and being in direct contact with the first conductive type first well region; a second conductive type third buried layer disposed in the first conductive type first well region and/or the first conductive type second well region; a second conductive type doped region disposed in the first conductive type second well region; a gate structure; a drain contact plug; and a source contact plug.
    Type: Application
    Filed: May 6, 2016
    Publication date: November 9, 2017
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chu-Feng CHEN, Wei-Chun CHOU, Chien-Wei CHIU