Patents by Inventor Wei-Chung Tseng
Wei-Chung Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240133427Abstract: An air-floating guide rail device includes a guide rail unit, a slider unit, and a linear motor unit. The guide rail unit includes a guide rail body and two air-floating block sets made of a material different from that of the guide rail body and each including top and side air-floating blocks. The slider unit includes a main sliding seat and two lateral sliding seats connected integrally to the main sliding seat and each having first and second guiding surfaces transverse to each other and disposed respectively adjacent to corresponding top and side air-floating blocks, and first and second air guiding passages connecting the first and second guiding surfaces to the external environment. The linear motor unit includes a stator and a mover mounted fixedly to the main sliding seat and movable relative to the stator for driving linear movement of the slider unit relative to the guide rail unit.Type: ApplicationFiled: December 20, 2022Publication date: April 25, 2024Inventors: KUN-CHENG TSENG, KUEI-TUN TENG, WEI-CHIH CHEN, WEN-CHUNG LIN
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Publication number: 20080305596Abstract: A method of fabricating a non-volatile memory is provided. A memory cell array having first memory units and second memory units is formed on a substrate. Then, a source region and a drain region are formed in the substrate on the respective sides of the memory cell array. Next, a patterned first inter-layer insulating layer is formed on the substrate to form a first trench and a number of second trenches. A conductive layer is formed on the substrate to form a source line in the first trench and conductive lines in the second trenches. A second inter-layer insulating layer is formed on the substrate and then a conductive plug having contact with the drain region is formed in the second inter-layer insulating layer and the first inter-layer insulating layer. Then, a bit line having contact with the conductive plug is formed on the second inter-layer insulating layer.Type: ApplicationFiled: August 24, 2008Publication date: December 11, 2008Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Houng-Chi Wei, Saysamone Pittikoun, Wei-Chung Tseng
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Patent number: 7445993Abstract: A method of fabricating non-volatile memory is provided. A plurality of first memory cells is formed on the memory cell region of a substrate. Each first memory cell comprises a first composite layer, a first gate and a cap layer. There is a gap between two adjacent first memory cells. Then, a plurality of gates is formed in the respective gaps. The gates together with a second composite layer form a plurality of second memory cells. The second memory cells and the first memory cells together constitute a memory cell column. In the meantime, a plurality of gate structures is also formed on the peripheral circuit region. The gates in the gaps and the gates in the peripheral circuit region are fabricated using different conductive layers.Type: GrantFiled: December 21, 2005Date of Patent: November 4, 2008Assignee: Powerchip Semiconductor Corp.Inventors: Wei-Chung Tseng, Houng-Chi Wei, Saysamone Pittikoun
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Patent number: 7442998Abstract: A method of fabricating a non-volatile memory is provided. A memory cell array having first memory units and second memory units is formed on a substrate. Then, a source region and a drain region are formed in the substrate on the respective sides of the memory cell array. Next, a patterned first inter-layer insulating layer is formed on the substrate to form a first trench and a plurality of second trenches. A conductive layer is formed on the substrate to form a source line in the first trench and conductive lines in the second trenches. A second inter-layer insulating layer is formed on the substrate and then a conductive plug having contact with the drain region is formed in the second inter-layer insulating layer and the first inter-layer insulating layer. Then, a bit line having contact with the conductive plug is formed on the second inter-layer insulating layer.Type: GrantFiled: September 18, 2005Date of Patent: October 28, 2008Assignee: Powerchip Semiconductor Corp.Inventors: Houng-Chi Wei, Saysamone Pittikoun, Wei-Chung Tseng
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Publication number: 20080259093Abstract: An electronic device is proposed for cooperating with a first electronic device to display a full image corresponding to a video signal. The electronic device includes a display screen for displaying a first partial image of the full image. The first electronic device includes a first display screen for displaying a second partial image of the full image. The electronic device further includes a control module for generating an adjust command and a transmitting module for transmitting the adjust command to the first electronic device in order to rotate the second partial image in such a manner that the second partial image combines with the first partial image to match the full image.Type: ApplicationFiled: April 15, 2008Publication date: October 23, 2008Applicant: Qisda CorporationInventor: Wei-Chung Tseng
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Patent number: 7285463Abstract: A method of fabricating a non-volatile memory is described. A plurality of first memory units having gaps between each other is formed over a substrate. Insulating spacers are formed on the sidewalls of the first memory units. A composite layer is formed on the substrate and the gaps between the first memory units are filled with a doped polysilicon layer. Thereafter, a portion of the doped polysilicon layer is removed to form trenches. After that, a metallic layer fills the trenches. A portion of the metallic layer is removed to form a plurality of gates. The gates and the composite layer together form a plurality of second memory units. The second memory units and the first memory units together constitute a memory cell column. Then, a source region and a drain region are formed in the substrate adjacent to the two sides of the memory cell column.Type: GrantFiled: November 10, 2006Date of Patent: October 23, 2007Assignee: Powerchip Semiconductor Corp.Inventors: Chien-Lung Chu, Saysamone Pittikoun, Houng-Chi Wei, Wei-Chung Tseng
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Patent number: 7285450Abstract: A method of fabricating non-volatile memory is provided. A plurality of first memory cells is formed on the memory cell region of a substrate. Each first memory cell includes a first composite layer, a first gate and a cap layer. There is a gap between two adjacent first memory cells. Then, a plurality of gates is formed in the respective gaps. The gates together with a second composite layer form a plurality of second memory cells. The second memory cells and the first memory cells together constitute a memory cell column. In the meantime, a plurality of gate structures is also formed on the peripheral circuit region. The gates in the gaps and the gates in the peripheral circuit region are formed using the same conductive layers.Type: GrantFiled: December 21, 2005Date of Patent: October 23, 2007Assignee: Powerchip Semiconductor Corp.Inventors: Wei-Chung Tseng, Houng-Chi Wei, Saysamone Pittikoun
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Patent number: 7226851Abstract: A method for manufacturing semiconductor device is provided. First, a substrate is provided. Then, a plurality of first gate lines disposed in parallel to each other and a first dummy gate line disposed in a direction perpendicular to the first gate lines are formed on the substrate. There is a first gap between the first dummy gate line and the first gate lines and there is a second gap between every pair of adjacent first gate lines. Thereafter, a second composite layer and a conductive layer are sequentially formed over the substrate. The conductive layer is etched back to form a plurality of second device structures that completely fills the second gaps. Then, the conductive layer in the first gap is removed.Type: GrantFiled: November 11, 2005Date of Patent: June 5, 2007Assignee: Powchip Semiconductor Corp.Inventors: Chien-Lung Chu, Wei-Chung Tseng, Saysamone Pittikoun, Houng-Chi Wei
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Publication number: 20070066008Abstract: A method of fabricating a non-volatile memory is described. A plurality of first memory units having gaps between each other is formed over a substrate. Insulating spacers are formed on the sidewalls of the first memory units. A composite layer is formed on the substrate and the gaps between the first memory units are filled with a doped polysilicon layer. Thereafter, a portion of the doped polysilicon layer is removed to form trenches. After that, a metallic layer fills the trenches. A portion of the metallic layer is removed to form a plurality of gates. The gates and the composite layer together form a plurality of second memory units. The second memory units and the first memory units together constitute a memory cell column. Then, a source region and a drain region are formed in the substrate adjacent to the two sides of the memory cell column.Type: ApplicationFiled: November 10, 2006Publication date: March 22, 2007Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Chien-Lung Chu, Saysamone Pittikoun, Houng-Chi Wei, Wei-Chung Tseng
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Patent number: 7166512Abstract: A method of fabricating a non-volatile memory is described. A plurality of first memory units having gaps between each other is formed over a substrate. Insulating spacers are formed on the sidewalls of the first memory units. A composite layer is formed on the substrate and the gaps between the first memory units are filled with a doped polysilicon layer. Thereafter, a portion of the doped polysilicon layer is removed to form trenches. After that, a metallic layer fills the trenches. A portion of the metallic layer is removed to form a plurality of gates. The gates and the composite layer together form a plurality of second memory units. The second memory units and the first memory units together constitute a memory cell column. Then, a source region and a drain region are formed in the substrate adjacent to the two sides of the memory cell column.Type: GrantFiled: August 11, 2005Date of Patent: January 23, 2007Assignee: Powerchip Semiconductor Corp.Inventors: Chien-Lung Chu, Saysamone Pittikoun, Houng-Chi Wei, Wei-Chung Tseng
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Publication number: 20060292850Abstract: A method for manufacturing semiconductor device is provided. First, a substrate is provided. Then, a plurality of first gate lines disposed in parallel to each other and a first dummy gate line disposed in a direction perpendicular to the first gate lines are formed on the substrate. There is a first gap between the first dummy gate line and the first gate lines and there is a second gap between every pair of adjacent first gate lines. Thereafter, a second composite layer and a conductive layer are sequentially formed over the substrate. The conductive layer is etched back to form a plurality of second device structures that completely fills the second gaps. Then, the conductive layer in the first gap is removed.Type: ApplicationFiled: November 11, 2005Publication date: December 28, 2006Inventors: Chien-Lung Chu, Wei-Chung Tseng, Saysamone Pittikoun, Houng-Chi Wei
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Publication number: 20060286749Abstract: A method of fabricating non-volatile memory is provided. A plurality of first memory cells is formed on the memory cell region of a substrate. Each first memory cell comprises a first composite layer, a first gate and a cap layer. There is a gap between two adjacent first memory cells. Then, a plurality of gates is formed in the respective gaps. The gates together with a second composite layer form a plurality of second memory cells. The second memory cells and the first memory cells together constitute a memory cell column. In the meantime, a plurality of gate structures is also formed on the peripheral circuit region. The gates in the gaps and the gates in the peripheral circuit region are fabricated using different conductive layers.Type: ApplicationFiled: December 21, 2005Publication date: December 21, 2006Inventors: Wei-Chung Tseng, Houng-Chi Wei, Saysamone Pittikoun
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Publication number: 20060286752Abstract: A method of fabricating non-volatile memory is provided. A plurality of first memory cells is formed on the memory cell region of a substrate. Each first memory cell includes a first composite layer, a first gate and a cap layer. There is a gap between two adjacent first memory cells. Then, a plurality of gates is formed in the respective gaps. The gates together with a second composite layer form a plurality of second memory cells. The second memory cells and the first memory cells together constitute a memory cell column. In the meantime, a plurality of gate structures is also formed on the peripheral circuit region. The gates in the gaps and the gates in the peripheral circuit region are formed using the same conductive layers.Type: ApplicationFiled: December 21, 2005Publication date: December 21, 2006Inventors: Wei-Chung Tseng, Houng-Chi Wei, Saysamone Pittikoun
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Publication number: 20060234446Abstract: A method of fabricating a non-volatile memory is provided. A memory cell array having first memory units and second memory units is formed on a substrate. Then, a source region and a drain region are formed in the substrate on the respective sides of the memory cell array. Next, a patterned first inter-layer insulating layer is formed on the substrate to form a first trench and a plurality of second trenches. A conductive layer is formed on the substrate to form a source line in the first trench and conductive lines in the second trenches. A second inter-layer insulating layer is formed on the substrate and then a conductive plug having contact with the drain region is formed in the second inter-layer insulating layer and the first inter-layer insulating layer. Then, a bit line having contact with the conductive plug is formed on the second inter-layer insulating layer.Type: ApplicationFiled: September 18, 2005Publication date: October 19, 2006Inventors: Houng-Chi Wei, Saysamone Pittikoun, Wei-Chung Tseng
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Publication number: 20060199333Abstract: A method of fabricating a non-volatile memory is described. A plurality of first memory units having gaps between each other is formed over a substrate. Insulating spacers are formed on the sidewalls of the first memory units. A composite layer is formed on the substrate and the gaps between the first memory units are filled with a doped polysilicon layer. Thereafter, a portion of the doped polysilicon layer is removed to form trenches. After that, a metallic layer fills the trenches. A portion of the metallic layer is removed to form a plurality of gates. The gates and the composite layer together form a plurality of second memory units. The second memory units and the first memory units together constitute a memory cell column. Then, a source region and a drain region are formed in the substrate adjacent to the two sides of the memory cell column.Type: ApplicationFiled: August 11, 2005Publication date: September 7, 2006Inventors: Chien-Lung Chu, Saysamone Pittikoun, Houng-Chi Wei, Wei-Chung Tseng