Abstract: An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.

Abstract: A photomask design correction method is provided. The photomask design correction method includes the following steps. A layer information data is provided. An OPC process is performed on the layer information data to obtain a first photomask data. A photomask is fabricated based on the first photomask data. A pattern information data of the photomask is obtained after the photomask is fabricated. The difference between the pattern information data and a database of the OPC process is analyzed. An OPC model of the OPC process is corrected based on the difference to obtain a corrected OPC model. The OPC process is performed using the corrected OPC model on the layer information data to obtain a second photomask data.

Abstract: An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.

Abstract: A pattern decomposition method including following steps is provided. A target pattern is provided, wherein the target pattern includes first patterns and second patterns alternately arranged, and the width of the second pattern is greater than the width of the first pattern. Each of the second patterns is decomposed into a third pattern and a fourth pattern, wherein the third pattern and the fourth pattern have an overlapping portion, and a pattern formed by overlapping the third pattern and the fourth pattern is the same as the second pattern. The third patterns and the first pattern adjacent to the fourth pattern are designated as first photomask patterns of a first photomask. The fourth patterns and the first pattern adjacent to the third pattern are designated as second photomask patterns of a second photomask.

Abstract: The present invention provides a method of designing a layout of a static random access memory (SRAM) pattern, the method includes the following steps: firstly, a target pattern is provided, and according to the target pattern, a plurality of first patterns and a first dummy pattern are formed in a substrate, the first pattern that disposed at the outermost boundary of the first patterns is defined as a first edge pattern, and the first dummy pattern is disposed adjacent to the first edge pattern, next, the first dummy pattern is removed, and afterwards, according to the target pattern, a plurality of second patterns are formed in the substrate, the second patterns comprises a second edge pattern that is disposed between the first edge pattern and an original position of the first dummy pattern.

Abstract: The present invention provides a method of designing a layout of a static random access memory (SRAM) pattern, the method includes the following steps: firstly, a target pattern is provided, and according to the target pattern, a plurality of first patterns and a first dummy pattern are formed in a substrate, the first pattern that disposed at the outermost boundary of the first patterns is defined as a first edge pattern, and the first dummy pattern is disposed adjacent to the first edge pattern, next, the first dummy pattern is removed, and afterwards, according to the target pattern, a plurality of second patterns are formed in the substrate, the second patterns comprises a second edge pattern that is disposed between the first edge pattern and an original position of the first dummy pattern.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.

Abstract: A method of manufacturing a semiconductor device includes: providing a semiconductor having active regions; depositing a dielectric layer on the semiconductor; forming a patterned etch mask on the dielectric layer; depositing a further dielectric layer on the dielectric layer and the patterned etch mask; planarizing the further dielectric layer until the patterned etch mask is exposed; and forming a further patterned etch mask having an opening on the further dielectric layer so that portions of the patterned etch mask are exposed from the opening.

Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.

Abstract: A mask inspecting method includes the following steps. A processing parameter is defined. An incident light is decided by the processing parameter. At least a portion of the incident light is emitted to and passes through a first position and a second position of a first area of a mask, to detect a first parameter and a second parameter respectively corresponding to the first position and the second position, and then the variation of the first parameter and the second parameter is compared. Additionally, at least a portion of the incident light is emitted to and passes through a third position and a fourth position of a second area of a mask, to detect a third parameter and a fourth parameter respectively corresponding to the third position and the fourth position, and then the variation of the third parameter and the fourth parameter is also compared.

Abstract: A mask inspecting method includes the following steps. A processing parameter is defined. An incident light is decided by the processing parameter. At least a portion of the incident light is emitted to and passes through a first position and a second position of a first area of a mask, to detect a first parameter and a second parameter respectively corresponding to the first position and the second position, and then the variation of the first parameter and the second parameter is compared. Additionally, at least a portion of the incident light is emitted to and passes through a third position and a fourth position of a second area of a mask, to detect a third parameter and a fourth parameter respectively corresponding to the third position and the fourth position, and then the variation of the third parameter and the fourth parameter is also compared.