Patents by Inventor Wei Daisy Cai
Wei Daisy Cai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7894243Abstract: In a first method of writing data to a resistive memory device (i.e. programming or erasing), successive electrical potentials are applied across the resistive memory device, wherein the successive electrical potentials are of increasing duration. In another method of writing data to a resistive memory device (i.e. programming or erasing), an electrical potential is applied across the resistive memory device, and the level of current through the memory device is sensed as the electrical potential is applied. The application of the electrical potential is ended based on a selected level of current through the resistive memory device.Type: GrantFiled: December 5, 2006Date of Patent: February 22, 2011Assignee: Spansion LLCInventors: Michael VanBuskirk, Wei Daisy Cai, Colin S. Bill, Yi-Ching Jean Wu
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Patent number: 7626882Abstract: A semiconductor memory device (104) selectably connectable to an external high voltage power supply (122) is provided. The semiconductor memory device (104) includes a switch (314), a detector (316) and a timing device (318). The switch (314) is connected to external voltage supply signals and selectably couples the external voltage supply signals to memory cells (305) of the semiconductor memory device (104) for memory operations thereof. The external voltage supply signals including a high voltage signal (412) provided from the external high voltage power supply (122) and an operational voltage signal Vcc (402). The detector (316) is connected to the external voltage supply signals for generating a timer activation signal (404) in response to detecting an operational voltage power-on period.Type: GrantFiled: December 20, 2006Date of Patent: December 1, 2009Assignee: Spansion LLCInventors: Nian Yang, Yonggang Wu, Aaron Lee, Wei Daisy Cai
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Patent number: 7474579Abstract: Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.Type: GrantFiled: December 20, 2006Date of Patent: January 6, 2009Assignee: Spansion LLCInventors: Colin S. Bill, Swaroop Kaza, Wei Daisy Cai, Tzu-Ning Fang, David Gaun, Eugen Gershon, Michael A. Van Buskirk, Jean Wu
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Patent number: 7450416Abstract: The present invention is a method of undertaking a procedure on a memory-diode, wherein a memory-diode is provided which is programmable so as to have each of a plurality of different threshold voltages. A reading of the state of the memory-diode indicates the so determined threshold voltage of the memory-diode.Type: GrantFiled: December 23, 2004Date of Patent: November 11, 2008Assignee: Spansion LLCInventors: Swaroop Kaza, Juri Krieger, David Gaun, Stuart Spitzer, Richard Kingsborough, Zhida Lan, Colin S. Bill, Wei Daisy Cai, Igor Sokolik
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Publication number: 20080151669Abstract: Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.Type: ApplicationFiled: December 20, 2006Publication date: June 26, 2008Applicant: SPANSION LLCInventors: Colin S. Bill, Swaroop Kaza, Wei Daisy Cai, Tzu-Ning Fang, David Gaun, Eugen Gershon, Michael A. Van Buskirk, Jean Wu
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Publication number: 20080151639Abstract: A semiconductor memory device (104) selectably connectable to an external high voltage power supply (122) is provided. The semiconductor memory device (104) includes a switch (314), a detector (316) and a timing device (318). The switch (314) is connected to external voltage supply signals and selectably couples the external voltage supply signals to memory cells (305) of the semiconductor memory device (104) for memory operations thereof. The external voltage supply signals including a high voltage signal (412) provided from the external high voltage power supply (122) and an operational voltage signal Vcc (402). The detector (316) is connected to the external voltage supply signals for generating a timer activation signal (404) in response to detecting an operational voltage power-on period.Type: ApplicationFiled: December 20, 2006Publication date: June 26, 2008Inventors: Nian Yang, Yonggang Wu, Aaron Lee, Wei Daisy Cai
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Publication number: 20080130381Abstract: In a first method of writing data to a resistive memory device (i.e. programming or erasing), successive electrical potentials are applied across the resistive memory device, wherein the successive electrical potentials are of increasing duration. In another method of writing data to a resistive memory device (i.e. programming or erasing), an electrical potential is applied across the resistive memory device, and the level of current through the memory device is sensed as the electrical potential is applied. The application of the electrical potential is ended based on a selected level of current through the resistive memory device.Type: ApplicationFiled: December 5, 2006Publication date: June 5, 2008Inventors: Michael VanBuskirk, Wei Daisy Cai, Colin S. Bill, Yi-Ching Jean Wu
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Patent number: 7355886Abstract: The present approach is a method of writing (which may be programming or erasing) data to a selected memory cell of a memory array. The array includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells each including a diode and a resistive memory device in series connecting a word line and a bit line, and a plurality of transistors, each having a first and second source/drain terminals and a gate, each transistor having a first source/drain terminal connected to a bit line. In the present method a voltage is applied to a selected word line, and a voltage is applied to the second source/drain terminal of a transistor having its first source/drain terminal connected to a selected bit line. The voltage applied to the selected word line is greater than the voltage applied to the second source/drain terminal of that transistor.Type: GrantFiled: December 5, 2006Date of Patent: April 8, 2008Assignee: Spansion LLCInventors: Wei Daisy Cai, Swaroop Kaza, Colin S. Bill, Michael VanBuskirk
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Patent number: 7259983Abstract: In the present method of programming and erasing the resistive memory devices of a memory device array, upon a single command, high current is provided in both the program and erase functions to program and erase only those memory devices whose state is to be changed from the previous state.Type: GrantFiled: May 27, 2005Date of Patent: August 21, 2007Assignee: Spansion LLCInventors: Colin S. Bill, Wei Daisy Cai
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Patent number: 7145824Abstract: Systems and methodologies are provided for temperature compensation of thin film diode voltage levels in memory sensing circuits. The subject invention includes a temperature sensitive bias circuit and an array core with a temperature variable select device. The array core can consist of a thin film diode in series with a nanoscale resistive memory cell. The temperature sensitive bias circuit can include a thin film diode in series with two resistors, and provides a temperature compensating bias voltage to the array core. The thin film diode of the temperature sensitive bias circuit tracks the diode of the array core, while the two resistors create a resistive ratio to mimic the effect of temperature and/or process variation(s) on the array core. The compensating bias reference voltage is generated by the temperature sensitive bias circuit, duplicated by a differential amplifier, and utilized to maintain a constant operation voltage level on the nanoscale resistive memory cell.Type: GrantFiled: March 22, 2005Date of Patent: December 5, 2006Assignee: Spansion LLCInventors: Colin S. Bill, Wei Daisy Cai
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Patent number: 7035141Abstract: The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor. The first and second diodes have different threshold voltages.Type: GrantFiled: November 17, 2004Date of Patent: April 25, 2006Inventors: Nicholas H. Tripsas, Colin S. Bill, Michael A. VanBuskirk, Matthew Buynoski, Tzu-Ning Fang, Wei Daisy Cai, Suzette Pangrle, Steven Avanzino