Patents by Inventor WEI (DAVID) PAN
WEI (DAVID) PAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250324951Abstract: A method for restoring a fish habitat water flow structure, including step 1: obtaining water body information and dividing a to-be-restored water area to obtain a plurality of investigation areas based on the water body information, by a water body information management unit; step 2: sampling and shooting aquatic organisms at a target location in the investigation areas by a shooting device of an aquatic organism investigation unit so as to obtain an aquatic organism sampling map, obtaining fish information in the water body based on the aquatic organism sampling map, by the aquatic organism investigation unit; step 3: selecting an optimal restoration plan for the fish habitat water flow structure based on fish information and water body information, by a habitat selection unit; step 4: restoring the target water area according to the optimal restoration plan, by a habitat restoration unit.Type: ApplicationFiled: August 17, 2024Publication date: October 23, 2025Inventors: WEI HUANG, JINJIN GE, MIN ZHANG, XIAOBO LIU, ZHUOWEI WANG, WEIJIE WANG, XIAODONG QU, HAIPING ZHANG, YANG YU, YING XIE
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Publication number: 20250325141Abstract: The disclosure provides an air heating cooker, including a main body and an oven door panel. A casing of the main body is provided with an accommodating space. The accommodating space has an accommodating opening on a same side as a cooking chamber opening. The oven door panel is slidably assembled in the accommodating space. The oven door panel, when in a second position of being drawn out of the accommodating space, is hinged with the casing and is flippable to cover the cooking chamber opening. When the oven door panel is not needed, the oven door panel is stored in the accommodating space.Type: ApplicationFiled: January 8, 2025Publication date: October 23, 2025Inventors: Yixin Zhan, Bo Wei
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Publication number: 20250326115Abstract: A method includes: accessing a toolpath and processing parameters—including a target force and feed rate—assigned to a region of a workpiece; and accessing a wear model representing abrasive degradation of a sanding pad arranged on a sanding head. The method also includes, during a processing cycle: accessing force values output by a force sensor 199 coupled to the sanding head; navigating the sanding head across the workpiece region according to the toolpath and, based on the force values deviating the sanding head from the toolpath to maintain forces of the sanding head on the workpiece region proximal the target force; accessing contact characteristics representing contact between the sanding pad and the workpiece; estimating abrasive degradation of the sanding pad based on the wear model and the sequence of contact characteristics; and modifying the set of processing parameters based on the abrasive degradation.Type: ApplicationFiled: June 30, 2025Publication date: October 23, 2025Inventors: Miguel A. Chavez-Garcia, Yi-Wei Chen, Cheng Gong, Shreyash Gotee, Rishav Guha, Satyandra K. Gupta, Shreeya Jain, Ariyan M. Kabir, Ceasar G. Navarro, Husein M. Noble, Alessandra B. Palacios Puga, Sagarkumar J. Panchal, Apoorva Patil, Pragadeeshkumar Rajavel, Brual C. Shah, Akshita Venkatachalam, Murilo M. Zelic
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Publication number: 20250325915Abstract: A toy figure is presented herein with a connector for coupling two parts of the toy figure together. The connector has a first connector portion, a second connector portion, and an intermediate connector portion located between and coupled to both the first connector portion and the second connector portion. The intermediate connector portion has two spaced apart middle portions that define a channel therebetween and which can move toward and away from each other. The first connector portion has two side portions that can also move toward and away from each other.Type: ApplicationFiled: December 11, 2024Publication date: October 23, 2025Inventors: Shixiong Huang, Wei Li, YunZhong Li, Qiu Ya Xiao, Peng Zhou
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Publication number: 20250330375Abstract: Disclosed embodiments receive an event stream from a remote capture agent. The event stream includes timestamped event data generated by the remote capture agent based on network traffic monitored by the remote capture agent. A graphical user interface (GUI) is caused to be displayed for obtaining configuration information for configuring the generation of time-series event data from network packets captured by the remote capture agent. A set of statistics is generated from the time-series event data, and the configuration information is updated to trigger subsequent storage and processing of at least a portion of the event stream by one or more components on a network based on one or more of the statistics, a storage limit associated with the time-series event data, an index volume of the event stream, a historical trend associated with the statistics, or input through the GUI.Type: ApplicationFiled: June 27, 2025Publication date: October 23, 2025Inventors: Fang I. HSIAO, Wei JIANG, Vladimir A. SHCHERBAKOV, Ramkumar CHANDRASEKHARAN, Clayton S. CHING
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Publication number: 20250329345Abstract: A magnetic stack includes a magnetic recording structure and at least two heat-sink layers where heat-sink layer located furthest from the magnetic recording structure has thermal conductivity equal to or greater than intervening heat-sink layers. One or more interlayers can be included in the magnetic stack. Data storage devices and systems including one or more of the magnetic stacks, and related methods.Type: ApplicationFiled: April 19, 2024Publication date: October 23, 2025Inventors: Wei-Heng Hsu, Pin-Wei Huang, YingGuo Peng, Yassine Quessab, Yue Hu, Florin Zavaliche, Ganping Ju, Daniel Staaks
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Publication number: 20250329719Abstract: A positive electrode sheet, a method for preparing the positive electrode sheet, and an application of the positive electrode sheet are provided. The positive electrode sheet includes a current collector and an electrode layer arranged on at least one side of the current collector. The electrode layer includes at least a first active material layer and a second active material layer which are arranged in a stacked manner. The first active material layer is in direct contact with a surface of the current collector. An active material in the first active material layer includes a layered oxide positive electrode material, and an active material in the second active material layer includes a manganese-based positive electrode material.Type: ApplicationFiled: June 29, 2025Publication date: October 23, 2025Applicant: EVE POWER CO., LTD.Inventors: Xiaodan SUN, Qi HU, Hanmin ZENG, Wei HE, Jincheng LIU
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Publication number: 20250330165Abstract: Embodiments of this application disclose a gating apparatus and a gating method, to implement a gating function in a simple structure and matching form. In this application, an example gating apparatus includes four main branches, M loading branches, M radio frequency switches, and four ports. The M radio frequency switches are all grounded, and M is equal to 2 or 4. The four main branches are sequentially connected end to end, and one of the four ports is disposed at a junction of any two connected main branches in the four main branches. When M is equal to 4, each of the four main branches is connected to one of the four loading branches, and each loading branch is connected to one of the M radio frequency switches.Type: ApplicationFiled: June 27, 2025Publication date: October 23, 2025Inventors: Xiaodong WEI, Tao PU, Weihong XIAO, Peifeng HU, Qiang HE
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Publication number: 20250329510Abstract: Forming an electrode structure includes forming a first cavity and a second cavity in a first hard mask layer, filling the first cavity and the second cavity with an electrically conductive material to form a first electrically conductive pillar and a second electrically conductive pillar; and planarizing exposed surfaces of the first and second electrically conductive pillars. Thereafter, a second hard mask layer is disposed on the first hard mask layer, a third cavity is formed passing through the second hard mask layer, and a second electroplating and planarization process fills the third cavity with the electrically conductive material to form a third electrically conductive pillar contacting the second electrically conductive pillar. A first electrode comprises the first electrically conductive pillar, and a second electrode comprises a combination of the second and third electrically conductive pillars.Type: ApplicationFiled: April 17, 2024Publication date: October 23, 2025Inventors: Yun-Chung Wu, Fu Wei Liu, Chia-Ai Chiu, Szu-Hsien Lee, Pei-Wei Lee
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Publication number: 20250329577Abstract: A method includes forming a well region in a substrate; forming a first implant region in the substrate, the first implant region; forming a second implant region in the well region; forming a first shallow trench isolation (STI) region in the substrate; forming first deep trench isolation (DTI) regions extending downwards from the first STI region into the well region; forming a second STI region in the substrate; forming second DTI regions extending downwards from the second STI region; forming a third STI region in the substrate; forming third DTI regions extending downwards from the third STI region; forming a gate electrode; forming a first source/drain region in the first implant region and in contact with the third STI region; and forming second source/drain region in the second implant region and between the first STI region and the second STI region.Type: ApplicationFiled: June 27, 2025Publication date: October 23, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Chieh FANG, Chien-Chang HUANG, Chi-Yuan WEN, Jian WU, Ming-Chi WU, Jung-Yu CHENG, Shih-Shiung CHEN, Wei-Tung HUANG, Yu-Lung YEH
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Publication number: 20250328987Abstract: Methods, systems, and non-transitory computer readable storage media are disclosed for generating digital images with a diffusion-based generative neural network conditioned on background-extracted lighting features. The disclosed system determines, in response to a request to generate a digital image, a target background image for inserting a foreground object into the target background image. The disclosed system generates, from the target background image and utilizing a lighting conditioning neural network, a lighting feature representation indicating one or more lighting parameters of the target background image. Additionally, the disclosed system generates, utilizing a diffusion-based generative neural network conditioned on the lighting feature representation, the digital image including the foreground object inserted into the target background image based on a composite image comprising the foreground object and the target background image with a foreground mask corresponding to the foreground object.Type: ApplicationFiled: April 19, 2024Publication date: October 23, 2025Inventors: Mengwei Ren, He Zhang, Wei Xiong, Zhixin Shu, Jae Shin Yoon, Jianming Zhang
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Publication number: 20250327316Abstract: A frame strip installation structure is provided, which includes a frame strip, an installation seat, and a connector. The frame strip has a cavity with an opening at a side, the installation seat is configured to be adhesively installed on a wall. The connector is respectively connected to the installation seat and the frame strip. The opening of the cavity faces the wall, both the installation seat and the connector are accommodated in the cavity. The connector has an adjustable state and a locking state. When the connector is in the adjustable state, the frame strip moves relative to the installation seat so as to adjust an installation position relative to the wall. When the connector is in the locking state, the frame strip is fixed relative to the installation seat. When the frame strip is installed against the wall, there is no need to drill holes in the wall.Type: ApplicationFiled: September 13, 2024Publication date: October 23, 2025Inventors: Wei Xu, Songhua Cao, Zizhang Li, Sijia Xu
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Publication number: 20250328345Abstract: A system-integrated solution for input/output device extended-control without operating system driver involvement is provided. In examples, systems and methods include receiving an out-of-band request from a human interface device, receiving an in-band request from the human interface device, and sending a signal directly to a peripheral device, via a micro-control unit, to honor the out-of-band request. In examples, the out-of-band request is received via an inter-integrated circuit.Type: ApplicationFiled: April 22, 2024Publication date: October 23, 2025Applicant: Microsoft Technology Licensing, LLCInventors: Yow-Wei CHENG, Sheng-Han TSAI, Yung-Jen CHEN
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Publication number: 20250328712Abstract: The present invention relates to a computer-implemented design synchronizing system (1) for designing floorplan of electronic systems.Type: ApplicationFiled: September 20, 2024Publication date: October 23, 2025Applicant: SKYECHIP SDN BHDInventors: Chin Choi Phaik, Eric Khoo Wey Ming
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Publication number: 20250330907Abstract: A client-side device and an improving method of jitter are provided. The client-side device includes an antenna, a memory and a processor. The antenna is wirelessly connected to a server and receives a packet from the server. The memory includes a playback latency buffer region. The processor is situated in CDRX and determines whether there is current jitter. When determining that there is the current jitter, the processor controls the playback latency buffer region to perform playback latency buffer processing on the packet and finds the DRX period corresponding to the current jitter, and the DRX period corresponding to the current jitter is a target period. The processor adjusts the wake-up time slot of the target period so that the wake-up time slot of the adjusted target period overlaps the time slot of the current jitter. By the aforementioned configuration, the reception success rate of the packet is improved.Type: ApplicationFiled: September 17, 2024Publication date: October 23, 2025Inventors: Guan Hsiung WANG, Wei Hsin CHEN
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Publication number: 20250330910Abstract: A method for a UE to monitor a PDCCH comprises receiving a first configuration from a base station to configure the UE with a first search space of the PDCCH, where the first search space is used for monitoring a scheduling signal used for indicating scheduling information, receiving a second configuration from the base station to configure the UE with a second search space of the PDCCH, wherein the second search space is used for monitoring a power saving signal used for indicating wake-up information associated with a DRX functionality, monitoring the first search space in response to the UE being in a DRX active time of the DRX functionality, wherein the DRX active time is a time during which the UE monitors the PDCCH, and not monitoring the second search space in response to the UE being in the DRX active time of the DRX functionality.Type: ApplicationFiled: May 13, 2025Publication date: October 23, 2025Inventors: Hsin-Hsi Tsai, Chia-Hung Wei, Chie-Ming Chou
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Publication number: 20250330996Abstract: The present application relates to devices and components including apparatus, systems, and methods to perform a non-codebook-based SRS transmission. In an example, eight or more SRS resources are used for the non-codebook-based SRS transmission. In this example, a base station configures the UE to use the eight or more SRS resources. Upon receiving an SRS transmission of the UE, the base station can send DCI to the UE to indicate an uplink resource allocation. This allocation can rely on precoding weights used for the eight or more SRS transmissions. The DCI can have a relatively reduced size for the resource allocation indication.Type: ApplicationFiled: April 6, 2023Publication date: October 23, 2025Applicant: Apple Inc.Inventors: Yushu Zhang, Dawei Zhang, Haitong Sun, Hong He, Huaning Niu, Seyed Ali Akbar Fakoorian, Sigen Ye, Wei Zeng, Weidong Yang
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Publication number: 20250331118Abstract: A riser card includes a circuit board and first, second, and third connectors. The first and second connectors are positioned at bottom and top edges of the circuit board, respectively. The third connector is mounted to a face of the circuit board. Such riser card may be mounted on a primary system board such that the first connector is detachably connected to a first complementary connector of the primary system board with the circuit board perpendicular to the primary system board, and the first connector receives power, data, and sideband signals from the first complementary connector. The second and third connectors may mate with second and third complementary connectors of an expansion card oriented parallel to the circuit board and a stackable secondary riser card oriented perpendicular to the circuit board, respectively. The riser card communicates power and sideband signals to the stackable secondary riser card via the third connector.Type: ApplicationFiled: April 22, 2024Publication date: October 23, 2025Inventors: Kuan-Wei Chen, Chih-Wei Chiang, Chao-Ming Chang
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Publication number: 20250331194Abstract: A ferroelectric capacitor structure including a first electrode, a second electrode, a first ferroelectric material layer, and a first nucleation layer is provided. The second electrode is located on the first electrode. The first ferroelectric material layer is located between the first electrode and the second electrode. The first nucleation layer is in contact with the first ferroelectric material layer. The material of the first nucleation layer is beta-tungsten (B-W).Type: ApplicationFiled: May 14, 2024Publication date: October 23, 2025Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Wei-Teng Hsu, Yu-Rui Chen, Wei-Jen Chen, Chee-Wee Liu
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Publication number: 20250331302Abstract: A semiconductor device includes a first semiconductor layer and a second semiconductor layer stacked vertically over a substrate. The first semiconductor layer and the second semiconductor layer extend laterally across the substrate. The semiconductor device includes a first gate structure and a second gate structure extending vertically from the substrate and perpendicular to the first semiconductor layer and the second semiconductor layer. The first gate structure engages the first semiconductor layer and the second semiconductor layer to form a first transistor and a second transistor, respectively. The second gate structure engages the first semiconductor layer and the second semiconductor layer to form a third transistor and a fourth transistor, respectively. The first gate structure is laterally adjacent to the second gate structure. The third transistor is an inactive transistor. The second transistor and the fourth transistor are active transistors.Type: ApplicationFiled: April 22, 2024Publication date: October 23, 2025Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Yang-Hsin Shih, Yi Wei Pan, Ying Chih Chen, Pin-Dai Sue, Kao-Cheng Lin