Abstract: A device includes: a complementary transistor including: a first transistor having first and second source/drain regions; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.

Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary method includes forming a dummy gate stack engaging a semiconductor fin over a substrate, conformally depositing a first dielectric layer over the substrate, conformally depositing a second dielectric layer over the first dielectric layer, etching back the first dielectric layer and the second dielectric layer to form a gate spacer extending along a sidewall surface of the dummy gate stack, the gate spacer comprising the first dielectric layer and the second dielectric layer, forming source/drain features in and over the semiconductor fin and adjacent the dummy gate stack, and replacing the dummy gate stack with a gate structure, where a dielectric constant of the first dielectric layer is less than a dielectric constant of silicon oxide, and the second dielectric layer is less easily to be oxidized than the first dielectric layer.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming an isolation structure to surround a lower portion of an active region, forming a gate stack across the active region, forming a trench through the gate stack, forming a conductive feature in the trench, depositing a metal material on a backside surface of the isolation structure, and planarizing the metal material, the isolation structure, the conductive feature, and the lower portion of the active region.

Abstract: A semiconductor device and the method of forming the same are provided. The semiconductor device may include a first source/drain region, a first nanostructure on a sidewall of the first source/drain region, a first gate structure around the first nanostructure, a first isolation region and a second isolation region on the first gate structure, and a dielectric layer over the first source/drain region and the first gate structure. The first isolation region and the second isolation region may each comprise a first dielectric material and a first dopant. The dielectric layer may extend between the first isolation region and the second isolation region. The dielectric layer may comprise a second dielectric material. The dielectric layer may be free of the first dopant.

Abstract: A method includes forming a lower transistor and an upper transistor over the lower transistor. The lower transistor comprises a lower source/drain region over a semiconductor substrate, and the lower source/drain region comprises a bottom side facing the semiconductor substrate. The upper transistor comprises an upper source/drain region over the lower source/drain region. The method further comprises forming a contact opening to expose the bottom side of the lower source/drain region, performing an epitaxy process to grow a semiconductor layer on the lower source/drain region, and forming a silicide layer electrically connected to the lower source/drain region through the semiconductor layer. By re-growing low-temperature epitaxy semiconductor layers from the backside of source/drain regions, the resistance of the lower source/drain regions and the respective contact resistance are reduced.

Abstract: A method includes forming a lower source/drain region over a substrate, forming a gate stack aside of the lower source/drain region, forming an upper source/drain region over the lower source/drain region, performing a backside thinning process to thin the substrate and to reveal a sacrificial region, removing the sacrificial region to reveal the lower source/drain region, and forming a backside contact plug to electrically connect to the lower source/drain region.

Abstract: A semiconductor device and the method of forming the same are provided. The semiconductor device may include an isolation region, a first dielectric layer over the isolation region, a second dielectric layer over the first dielectric layer, a first source/drain region in the second dielectric layer, a first nanostructure on a sidewall of the first source/drain region, a first gate electrode around the first nanostructure, a first source/drain contact over the first source/drain region electrically connected to the first source/drain region, a conductive feature in the first dielectric layer and the isolation region, and a dielectric feature over the conductive feature and in the second dielectric layer. A first portion of the first source/drain contact may be between two inner sidewalls of the dielectric feature, and the first portion of the first source/drain contact may be electrically connected to the conductive feature.

Abstract: A semiconductor device includes: a first substrate; a first fin protruding above the first substrate; first nanostructures over the first fin; a first gate structure around the first nanostructures; a first source/drain region adjacent to the first gate structure and contacting a first subset of the first nanostructures; a first dielectric structure between the first source/drain region and the first fin, where the first dielectric structure contacts a second subset of the first nanostructures; second nanostructures over the first fin and laterally spaced apart from the first nanostructures; a second gate structure around the second nanostructures; and a second source/drain region adjacent to the second gate structure and contacting the second nanostructures.

Abstract: In an embodiment, a method includes forming a multi-layer stack over a semiconductor substrate, patterning the multi-layer stack and the semiconductor substrate to form a fin structure, the fin structure including alternating semiconductor nanostructures and dummy nanostructures, where a bottommost dummy nanostructure of the dummy nanostructures has a first thickness, where first dummy nanostructures of the dummy nanostructures are disposed above the bottommost dummy nanostructure, and each of the first dummy nanostructures has a second thickness that is smaller than the first thickness, forming source/drain recesses in the fin structure, etching sidewalls of the first dummy nanostructures and the bottommost dummy nanostructure in the source/drain recesses to form sidewall recesses, forming inner spacers in the sidewall recesses in the first dummy nanostructures and the bottommost dummy nanostructure, and replacing the first dummy nanostructures and the bottommost dummy nanostructure with a gate structure.

Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.

Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary method includes forming a dummy gate stack engaging a semiconductor fin over a substrate, conformally depositing a first dielectric layer over the substrate, conformally depositing a second dielectric layer over the first dielectric layer, etching back the first dielectric layer and the second dielectric layer to form a gate spacer extending along a sidewall surface of the dummy gate stack, the gate spacer comprising the first dielectric layer and the second dielectric layer, forming source/drain features in and over the semiconductor fin and adjacent the dummy gate stack, and replacing the dummy gate stack with a gate structure, where a dielectric constant of the first dielectric layer is less than a dielectric constant of silicon oxide, and the second dielectric layer is less easily to be oxidized than the first dielectric layer.

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: A method includes forming a multi-layer stack comprising dummy layers and semiconductor layers located alternatingly, and forming a plurality of dummy gate stacks on sidewalls and a top surface of the multi-layer stack. Two of the plurality of dummy gate stacks are immediately neighboring each other, and have a space in between. A first source/drain region and a second source/drain region are formed in the multi-layer stack, with the second source/drain region overlapping the first source/drain region. The method further includes replacing the plurality of dummy gate stacks with a plurality of replacement gate stacks, replacing a first one of the plurality of replacement gate stacks with a first dielectric isolation region, forming a deep contact plug in the space, forming a front-side via over the deep contact plug, and forming a back-side via under the deep contact plug.

Abstract: In an embodiment, a semiconductor device may include a plurality of first nanostructures. The plurality of first nanostructures extend between first source/drain regions. The semiconductor device may also include a plurality of second nanostructures over the plurality of first nanostructures. The plurality of second nanostructures extend between second source/drain regions. The device may furthermore include a first gate stack around the plurality of first nanostructures. The device may in addition include a second gate stack over the first gate stack and disposed around the plurality of second nanostructures. The device may moreover include a vertical interconnect structure extending through the first and second gate stacks. The device may also include a frontside contact electrically coupled to a frontside of the vertical interconnect structure and a backside contact electrically coupled to a backside of the vertical interconnect structure.

Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.

Abstract: A semiconductor device includes a backside gate etch stop layer (ESL) on a backside of a first gate stack, wherein a plurality of first nanostructures overlaps the backside gate ESL. The backside gate ESL may comprise a high-k dielectric material. The semiconductor device further includes the plurality of first nanostructures extending between first source/drain regions and a plurality of second nanostructures over the plurality of first nanostructures and extending between second source/drain regions. A first gate stack is disposed around the plurality of first nanostructures, and a second gate stack over the first gate stack is disposed around the plurality of second nanostructures. A backside gate contact extends through the backside gate ESL to be electrically coupled to the first gate stack.

Abstract: A method includes forming a first transistor and a second transistor over a semiconductor substrate, wherein the first transistor and the second transistor are vertically stacked. The method further includes exposing a backside of a first gate stack of the first transistor; forming a backside gate etch stop layer (ESL) on the backside of the first gate stack; patterning a contact opening through the backside gate ESL to expose the first gate stack; and forming a backside gate contact in the contact opening. The backside gate contact extends through the backside gate ESL to electrically connect to the first gate stack.

Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.

Abstract: In an embodiment, a semiconductor device may include a plurality of first nanostructures. The plurality of first nanostructures extend between first source/drain regions. The semiconductor device may also include a plurality of second nanostructures over the plurality of first nanostructures. The plurality of second nanostructures extend between second source/drain regions. The device may furthermore include a first gate stack around the plurality of first nanostructures. The device may in addition include a second gate stack over the first gate stack and disposed around the plurality of second nanostructures. The device may moreover include a vertical interconnect structure extending through the first and second gate stacks. The device may also include a frontside contact electrically coupled to a frontside of the vertical interconnect structure and a backside contact electrically coupled to a backside of the vertical interconnect structure.