Abstract: A wafer (18) is made using a mask (14) that has a quartz substrate (15) and a patterned stack (32) for providing a mask pattern. The patterned stack comprises an opaque layer (36) between two ARC layers (34, 38). The patterned stack reduces flare, which in turn improves critical dimension (CD) control. The stack reduces the reflections that come from the interface between the opaque layer (36) and quartz substrate (15). This stack also absorbs the reflections that come back from the direction of the wafer. The opaque layer (36) is silicon, which is opaque at wavelengths below 300 nanometers, and the ARC layers are non-stoichiometric silicon nitride.

Abstract: A photomask and a method for making the same in which an opaque feature (38) is formed on a transparent substrate (32) and a depression (44) is etched in the transparent substrate (32) adjacent to the opaque feature (38). The depression (44) is etched to a depth such that a phase difference between light passing through the substrate (32) outside the depression (44) and light passing through the depression is 180°. In one embodiment, the depression (44) is formed in the substrate directly adjacent to an edge of the opaque feature (38). In another embodiment, the depression (58) surrounds a mesa structure (59) formed in the substrate (50), and the opaque feature (62) resides on the mesa structure (59). The depression (58) may be laterally spaced from an edge of the opaque feature (62).

Abstract: A semiconductor device is formed by patterning a resist layer using a rim phase shifting mask. A multilayer or single patterning layer to form the different phase-shifting regions and opaque regions is used to manufacture the rim phase shifting mask. First phase shifting regions are formed by transferring an opening in the multilayer or single patterning layer through an opaque layer and a transparent substrate. At least portions of the same multilayer or single patterning layer are used to recess the opaque layer a predetermined distance to form rims (second phase shifting regions). The first phase-shifting regions phase shift the light traveling through them 180 degrees relative to the light traveling through the rims, thereby increasing the contrast of the light traveling through the rim phase shifting mask.

Abstract: A manufacturing technique for making grating features utilizes the etching characteristics for photoresist to provide desirable geometric shapes in close proximity to each other. This results in a grating for optocoupling, which is manufacturable and provides efficient coupling. A silicon waveguide is conveniently achieved using a SOI substrate so that the insulator underlying the silicon provides one material adjoining the silicon with a lower index of refraction than silicon. The top surface of the silicon has the desirable geometric shapes that result also in a lower index of refraction than silicon above the main body of the silicon substrate.

Abstract: A manufacturing technique for making grating features utilizes the etching characteristics for photoresist to provide desirable geometric shapes in close proximity to each other. This results in a grating for optocoupling, which is manufacturable and provides efficient coupling. A silicon waveguide is conveniently achieved using a SOI substrate so that the insulator underlying the silicon provides one material adjoining the silicon with a lower index of refraction than silicon. The top surface of the silicon has the desirable geometric shapes that result also in a lower index of refraction than silicon above the main body of the silicon substrate.

Abstract: An optical device uses one or more doped pockets in one embodiment to increase the electric field at one or more edges of the light absorbing region to increase the efficiency of the optical device. In alternate embodiments, the optical device uses an overlying light-barrier layer to reduce optical absorption within the more highly doped region. Some embodiments use a comb-like structure for the optical device to reduce capacitance and create a planar CMOS compatible structure.

Abstract: A method and apparatus for characterizing processing operations is presented. Following exposure of a wafer to plasma, the surface charge distribution pattern on the wafer is measured. The surface charge distribution pattern on the wafer is then compared with known surface charge distribution patterns to determine if the measured charge distribution pattern correlates to desirable patterns associated with successful performance of one or more processing steps. In some embodiments, the comparison of the measured charge distribution pattern can be used to detect specific problems in one or more processing steps such that corrective action can be taken in a timely manner. The comparison between the measured charge distribution pattern and known charge distribution patterns may be performed using image comparison or using quantitative comparisons based on charge levels measured within each pattern.

Abstract: A process for fabricating refractory-metal silicide layers in a semiconductor device includes the formation of a composite gate electrode (54) and a buried contact structure (56). The composite gate electrode (54) includes a refractory-metal silicide layer (52) separated from a first polycrystalline silicon layer (38) by a diffusion barrier layer (46). The buried contact structure (56) includes a refractory-metal silicide layer (52) separated from a buried contact region (44) of a semiconductor substrate (30) by the diffusion barrier layer (46). The refractor-metal silicide layer (52) is formed by inverting a second polycrystalline silicon layer (48) to a refractory-metal silicide material while preventing the diffusion of refractory-metal atoms into underlying silicon regions.