Patents by Inventor Wei-Fan Lee

Wei-Fan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250028143
    Abstract: A driving mechanism for moving an optical element is provided, including a fixed part, a movable part, a driving assembly, and a first guiding member connected between the fixed part and the movable part. The optical element is disposed on the movable part, and the driving assembly drives the movable part to move relative to the fixed part. The first guiding member is configured for guiding the movable part to move relative to the fixed part.
    Type: Application
    Filed: July 10, 2024
    Publication date: January 23, 2025
    Inventors: Po-Xiang ZHUANG, Yi-Fan LEE, Chao-Yuan CHANG, Wei-Jhe SHEN, Sin-Jhong SONG, Kun-Shih LIN, Yi-Ho CHEN, Chao-Chang HU
  • Publication number: 20240297254
    Abstract: A method of manufacturing a semiconductor device includes forming a fin structure protruding from a first isolation insulating layer disposed over a substrate, and forming a dummy gate structure over an upper portion of the fin structure. The method further includes forming a second isolation insulating layer over the first isolation insulating layer and forming gate sidewall spacers on opposing side faces of the dummy gate structure. The method also includes after the gate sidewall spacers are formed, forming a trench by etching a source/drain region of the fin structure and forming a base semiconductor epitaxial layer in the trench. The method further includes forming a cap semiconductor epitaxial layer on the base semiconductor epitaxial layer 108, removing the dummy gate structure to expose the fin structure, and forming a gate dielectric layer over a channel region of the fin structure.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsien TU, Wei-Fan LEE
  • Patent number: 12021144
    Abstract: A semiconductor device includes a fin structure protruding from a first isolation insulating layer provided over a substrate, a gate dielectric layer disposed over a channel region of the fin structure, a gate electrode layer disposed over the gate dielectric layer, a base semiconductor epitaxial layer disposed over a source/drain region of the fin structure, and a cap semiconductor epitaxial layer disposed over the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a different lattice constant than the base semiconductor epitaxial layer, and a surface roughness of the cap semiconductor epitaxial layer along a source-to-drain direction is greater than zero and smaller than a surface roughness of the base semiconductor epitaxial layer along the source-to-drain direction.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Hsien Tu, Wei-Fan Lee
  • Patent number: 11600728
    Abstract: The present disclosure is directed to source/drain (S/D) epitaxial structures with enlarged top surfaces. In some embodiments, the S/D epitaxial structures include a first crystalline epitaxial layer comprising facets; a non-crystalline epitaxial layer on the first crystalline layer; and a second crystalline epitaxial layer on the non-crystalline epitaxial layer, where the second crystalline epitaxial layer is substantially facet-free.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: March 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Hsien Tu, Wei-Fan Lee
  • Publication number: 20220376067
    Abstract: The present disclosure is directed to source/drain (S/D) epitaxial structures with enlarged top surfaces. In some embodiments, the S/D epitaxial structures include a first crystalline epitaxial layer comprising facets; a non-crystalline epitaxial layer on the first crystalline layer; and a second crystalline epitaxial layer on the non-crystalline epitaxial layer, where the second crystalline epitaxial layer is substantially facet-free.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 24, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Hsien Tu, Wei-Fan Lee
  • Publication number: 20220130993
    Abstract: A semiconductor device includes a fin structure protruding from a first isolation insulating layer provided over a substrate, a gate dielectric layer disposed over a channel region of the fin structure, a gate electrode layer disposed over the gate dielectric layer, a base semiconductor epitaxial layer disposed over a source/drain region of the fin structure, and a cap semiconductor epitaxial layer disposed over the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a different lattice constant than the base semiconductor epitaxial layer, and a surface roughness of the cap semiconductor epitaxial layer along a source-to-drain direction is greater than zero and smaller than a surface roughness of the base semiconductor epitaxial layer along the source-to-drain direction.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Inventors: Wen-Hsien TU, Wei-Fan LEE
  • Patent number: 11222980
    Abstract: A semiconductor device includes a fin structure protruding from a first isolation insulating layer provided over a substrate, a gate dielectric layer disposed over a channel region of the fin structure, a gate electrode layer disposed over the gate dielectric layer, a base semiconductor epitaxial layer disposed over a source/drain region of the fin structure, and a cap semiconductor epitaxial layer disposed over the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a different lattice constant than the base semiconductor epitaxial layer, and a surface roughness of the cap semiconductor epitaxial layer along a source-to-drain direction is greater than zero and smaller than a surface roughness of the base semiconductor epitaxial layer along the source-to-drain direction.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Hsien Tu, Wei-Fan Lee
  • Publication number: 20210391454
    Abstract: The present disclosure is directed to source/drain (S/D) epitaxial structures with enlarged top surfaces. In some embodiments, the S/D epitaxial structures include a first crystalline epitaxial layer comprising facets; a non-crystalline epitaxial layer on the first crystalline layer; and a second crystalline epitaxial layer on the non-crystalline epitaxial layer, where the second crystalline epitaxial layer is substantially facet-free.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: WEN-HSIEN TU, Wei-Fan LEE
  • Publication number: 20210020770
    Abstract: A semiconductor device includes a fin structure protruding from a first isolation insulating layer provided over a substrate, a gate dielectric layer disposed over a channel region of the fin structure, a gate electrode layer disposed over the gate dielectric layer, a base semiconductor epitaxial layer disposed over a source/drain region of the fin structure, and a cap semiconductor epitaxial layer disposed over the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a different lattice constant than the base semiconductor epitaxial layer, and a surface roughness of the cap semiconductor epitaxial layer along a source-to-drain direction is greater than zero and smaller than a surface roughness of the base semiconductor epitaxial layer along the source-to-drain direction.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 21, 2021
    Inventors: Wen-Hsien TU, Wei-Fan LEE
  • Patent number: 9721827
    Abstract: One or more semiconductor arrangements are provided. The semiconductor arrangements include a buried layer over a well, a dielectric layer over the buried layer, a first gate stack over the dielectric layer and a S/D region disposed proximate the first gate stack. The S/D region has a first tip proximity region that extends under the first gate stack. One or more methods of forming a semiconductor arrangement are also provided. The methods include forming a S/D recess in at least one of a dielectric layer, a buried layer or a well, wherein the S/D recess is proximate a first gate stack and has a first recess tip proximity region that extends under the first gate stack as a function of the buried layer, and forming a S/D region in the S/D recess such that the S/D region has a first tip proximity region that extends under the first gate stack.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: August 1, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Wei-Fan Lee, Yuan-feng Chao, Yen Chuang
  • Patent number: 9595593
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and an interfacial layer formed over the substrate. The semiconductor structure further includes a gate structure formed over the interfacial layer. In addition, the interfacial layer is made of metal germanium oxide, metal silicon oxide, or metal germanium silicon oxide and is in direct contact with a top surface of the substrate.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: March 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Fan Lee, Chee-Wee Liu, Chin-Kun Wang, Yuh-Ta Fan, Chih-Hsiung Huang, Tzu-Yao Lin
  • Publication number: 20160380069
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and an interfacial layer formed over the substrate. The semiconductor structure further includes a gate structure formed over the interfacial layer. In addition, the interfacial layer is made of metal germanium oxide, metal silicon oxide, or metal germanium silicon oxide and is in direct contact with a top surface of the substrate.
    Type: Application
    Filed: June 29, 2015
    Publication date: December 29, 2016
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Wei-Fan LEE, Chee-Wee LIU, Chin-Kun WANG, Yuh-Ta FAN, Chih-Hsiung HUANG, Tzu-Yao LIN
  • Publication number: 20150243785
    Abstract: One or more semiconductor arrangements are provided. The semiconductor arrangements include a buried layer over a well, a dielectric layer over the buried layer, a first gate stack over the dielectric layer and a S/D region disposed proximate the first gate stack. The S/D region has a first tip proximity region that extends under the first gate stack. One or more methods of forming a semiconductor arrangement are also provided. The methods include forming a S/D recess in at least one of a dielectric layer, a buried layer or a well, wherein the S/D recess is proximate a first gate stack and has a first recess tip proximity region that extends under the first gate stack as a function of the buried layer, and forming a S/D region in the S/D recess such that the S/D region has a first tip proximity region that extends under the first gate stack.
    Type: Application
    Filed: February 27, 2014
    Publication date: August 27, 2015
    Inventors: Wei-Fan Lee, Yuan-feng Chao, Yen Chuang