Abstract: A multilayer printed circuit board includes an inner circuit layer, a first outer circuit layer, a second outer circuit layer, a via, and a layer of high dielectric dissipation solder resist ink. The first outer circuit layer includes a first trace for transmitting a high frequency signal. The inner circuit layer includes a second trace, and is formed between the first outer circuit layer and the second outer circuit layer. The via is formed from the first outer circuit layer to the second outer circuit layer, and is coupled to the first trace and the second trace. The second trace is coupled to the first trace through the via for transmitting the high frequency signal. The layer of high dielectric dissipation solder resist ink is formed on a terminal of the open stub of the via exposed outside of the second outer circuit layer.

Abstract: A test probe is provided. The test probe includes a group of shielding boards and two probe pins. The group of shielding boards has two opposite surfaces. The group of shielding boards includes at least two insulation boards and at least one metal board. The metal board is formed between the two insulation boards. The two probe pins are formed on the two surfaces of the group of shielding boards and have a distance between each other.

Abstract: A test probe is provided. The test probe includes a group of shielding boards and two probe pins. The group of shielding boards has two opposite surfaces. The group of shielding boards includes at least two insulation boards and at least one metal board. The metal board is formed between the two insulation boards. The two probe pins are formed on the two surfaces of the group of shielding boards and have a distance between each other.

Abstract: The reworkable bonding pad layout includes a first point, a second point, a reworkable bonding pad, a first leading wire, and a second leading wire. There is a debug position defined between the first point and the second point. The reworkable bonding pad is formed at the debug position. The first leading wire may connect the reworkable bonding pad and the first point. The second leading wire may connect the reworkable bonding pad and the second point. The reworkable bonding pad is cut into a first debug area connecting with the first leading wire, and a second debug area connecting with the second leading wire.

Abstract: A data processing system and method is proposed. The data processing system is connected with a component library and an original design database. The component library includes component data including part numbers and attributes of components while the original design database stores original design data of pins, nets and codes containing part numbers of components on a circuit diagram. A setting module allows users to set instructions of the original design data to be extracted, and then a data extracting module extracts data of pins, nets and codes of components from the original design database based on these instructions, so that a data processing module may analyze and associate the data extracted by the data extracting module with the component data in the component library and integrates the associated data to create an integrated data required by the user.

Abstract: A data processing system and method is proposed. The data processing system is connected with a component library and an original design database. The component library includes component data including part numbers and attributes of components while the original design database stores original design data of pins, nets and codes containing part numbers of components on a circuit diagram. A setting module allows users to set instructions of the original design data to be extracted, and then a data extracting module extracts data of pins, nets and codes of components from the original design database based on these instructions, so that a data processing module may analyze and associate the data extracted by the data extracting module with the component data in the component library and integrates the associated data to create an integrated data required by the user.

Abstract: A window operation menu for graphically revising an electrical constraint set and a method of using the same. It may be used to graphically preview and revise the attribute contents of the electrical constraint set analyzed and exported by the wiring software, so that the batch revisions can be performed simultaneously for the attribute names of a plurality of electrical constraint sets, thus allowing the user to utilize the previously designed electrical constraint sets repeatedly. This achieves the purpose of saving the time and effort spent on the design and development of electronic products.

Abstract: A system and method of generating an auto-wiring script, which can be utilized to generate a script used exclusively for the wiring software according to corresponding table specifying the relations between the net names and the electrical constraint sets and the files of other related attributes. The wiring software can be used to perform automatic circuit design by making use of said script, and the errors may be corrected real time according to the error messages caused by applying said auto-wiring script on the newly designed circuit board design drawing file.

Abstract: A window operation menu for graphically revising an electrical constraint set and a method of using the same. It may be used to graphically preview and revise the attribute contents of the electrical constraint set analyzed and exported by the wiring software, so that the batch revisions can be performed simultaneously for the attribute names of a plurality of electrical constraint sets, thus allowing the user to utilize the previously designed electrical constraint sets repeatedly. This achieves the purpose of saving the time and effort spent on the design and development of electronic products.

Abstract: An assisted generating system and method for layout data conversions converts an output file generated by a circuit design program (such as ConceptHDL). In addition to rule setting, the method automatically adjusts fields with abnormal properties. It provides a user interface with hints for the user to edit the contents. The system finally outputs a converted file compatible with a circuit layout program (such as Allegro) to assist subsequent layout designs.