Patents by Inventor Wei Feig Qu
Wei Feig Qu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8575722Abstract: A method for producing a semiconductor wafer having a multilayer film, in production of a semiconductor device by the steps of forming a porous layer on a surface of a semiconductor wafer by changing a surface portion into the porous layer, forming a semiconductor film on a surface of the porous layer to produce a semiconductor wafer having a multilayer film, fabricating a device on the semiconductor film, and producing the semiconductor device by delaminating the semiconductor film along the porous layer, the semiconductor film having the device formed thereon, including flattening the semiconductor wafer after delaminating and reusing the flattened semiconductor wafer, the method further including a thickness adjusting step of adjusting a whole thickness of the semiconductor wafer having a multilayer film to be produced by reusing the semiconductor wafer so as to satisfy a predetermined standard.Type: GrantFiled: December 8, 2009Date of Patent: November 5, 2013Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Kiyoshi Mitani, Tsuyoshi Ohtsuki, Toru Takahashi, Wei Feig Qu
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Publication number: 20110266655Abstract: A method for producing a semiconductor wafer having a multilayer film, in production of a semiconductor device by the steps of forming a porous layer on a surface of a semiconductor wafer by changing a surface portion into the porous layer, forming a semiconductor film on a surface of the porous layer to produce a semiconductor wafer having a multilayer film, fabricating a device on the semiconductor film, and producing the semiconductor device by delaminating the semiconductor film along the porous layer, the semiconductor film having the device formed thereon, including flattening the semiconductor wafer after delaminating and reusing the flattened semiconductor wafer, the method further including a thickness adjusting step of adjusting a whole thickness of the semiconductor wafer having a multilayer film to be produced by reusing the semiconductor wafer so as to satisfy a predetermined standard.Type: ApplicationFiled: December 8, 2009Publication date: November 3, 2011Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Kiyoshi Mitani, Tsuyoshi Ohtsuki, Toru Takahashi, Wei Feig Qu
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Publication number: 20090197396Abstract: The present invention provides a method for producing a silicon wafer at least including a step of performing RTA heat treatment with respect to a silicon wafer in an atmospheric gas, wherein nitrogen gas is used as the atmospheric gas, which is mixed with oxygen at a concentration of less than 100 ppm so as to perform the heat treatment. Hereby a method for producing a high-quality wafer can be provided, where the RTA heat treatment subject to the silicon wafer can be performed at a low temperature or over a short period of time, so that generation of slip dislocation of the silicon wafer can be suppressed, and at the same time vacancies can be implanted inside the silicon wafer without using NH3.Type: ApplicationFiled: May 24, 2007Publication date: August 6, 2009Applicant: Shin-Etsu Handotai Co., Ltd.Inventor: Wei Feig Qu
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Patent number: 7189293Abstract: The present invention is a method of producing an annealed wafer wherein a silicon single crystal wafer having a diameter of 200 mm or more produced by the Czochralski (CZ) method is subjected to a high temperature heat treatment in an atmosphere of an argon gas, a hydrogen gas, or a mixture gas thereof at a temperature of 1100–1350° C. for 10–600 minutes, and before the high temperature heat treatmen, a pre-annealing is performed at a temperature less than the temperature of the high temperature heat treatment, so that the growth of slip dislocations is suppressed by growing oxide precipitates. Thereby, there is provided a method of producing an annealed wafer wherein the generation and growth of slip dislocations generated in a high temperature heat treatment are suppressed and the defect density in the wafer surface layer is lowered even in the case of a silicon single crystal wafer having a large diameter of 200 mm or more, and the annealed wafer.Type: GrantFiled: June 25, 2002Date of Patent: March 13, 2007Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya, Wei Feig Qu, Hiroshi Takeno, Ken Aihara
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Patent number: 7153785Abstract: The present invention provides method of producing an annealed wafer wherein a silicon single crystal wafer produced by the Czochralski (CZ) method is subjected to a high temperature annealing in an atmosphere of an argon gas, a hydrogen gas, or a mixture gas thereof at a temperature of 1100–1350° C. for 10–600 minutes, during the annealing the silicon single crystal wafer is supported by a supporting jig only in a central side region of the wafer except for 5 mm or more from a peripheral end of the wafer, and before performing the high temperature annealing, a pre-annealing is performed at a temperature less than the temperature of the high temperature annealing to grow oxide precipitates. Thereby, there is provided a method of producing an annealed wafer wherein slip dislocations generated in a high temperature annealing can be suppressed even in the case of a silicon single crystal wafer having a large diameter of 300 mm or more, and provided the annealed wafer.Type: GrantFiled: August 23, 2002Date of Patent: December 26, 2006Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya, Wei Feig Qu
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Patent number: 7147711Abstract: The present invention provides a method for producing a silicon wafer, which comprises growing a silicon single crystal ingot having a resistivity of 100 ?·cm or more and an initial interstitial oxygen concentration of 10 to 25 ppma and doped with nitrogen by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to a heat treatment so that a residual interstitial oxygen concentration in the wafer should become 8 ppma or less, and a method for producing a silicon wafer, which comprises growing a silicon single crystal ingot having a resistivity of 100 ?·cm or more and an initial interstitial oxygen concentration of 8 ppma or less and doped with nitrogen by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to a heat treatment to form an oxide precipitate layer in a bulk portion of the wafer, as well as silicon wafers produced by these production methods.Type: GrantFiled: September 14, 2001Date of Patent: December 12, 2006Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Masaro Tamatsuka, Wei Feig Qu, Norihiro Kobayashi
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Patent number: 6858094Abstract: The present invention provides a silicon wafer having a DZ layer near a surface and an oxide precipitate layer in a bulk portion, wherein interstitial oxygen concentrations of the DZ layer, the oxide precipitate layer and a transition region between the DZ layer and the oxide precipitate layer are all 8 ppma or less, and an epitaxial silicon wafer, wherein an epitaxial layer is formed on a surface of the silicon wafer, as well as a method for producing a silicon wafer, which comprises growing a silicon single crystal ingot having an initial interstitial oxygen concentration of 10 to 25 ppma by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to a first heat treatment at 950 to 1050° C. for 2 to 5 hours, a second heat treatment at 450 to 550° C. for 4 to 10 hours, a third heat treatment at 750 to 850° C. for 2 to 8 hours, and a fourth heat treatment at 950 to 1100° C. for 8 to 24 hours.Type: GrantFiled: September 14, 2001Date of Patent: February 22, 2005Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Wei Feig Qu, Yoshinori Hayamizu, Hiroshi Takeno
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Patent number: 6841450Abstract: The present invention provides an annealed wafer manufacturing method using a heat treatment method causing no change in resistivity of a wafer surface even when a silicon wafer having boron deposited on a surface thereof from an environment is subjected to heat treatment in an insert gas atmosphere and enabling the heat treatment in an ordinary diffusion furnace not requiring a sealed structure for increasing airtightness nor any specific facility such as explosion-proof facility. The present invention also provides an annealed wafer in which a boron concentration in the vicinity of a surface thereof is constant and crystal defects are annihilated.Type: GrantFiled: September 18, 2001Date of Patent: January 11, 2005Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya, Wei Feig Qu, Makoto Iida
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Publication number: 20040231759Abstract: The present invention is a method of producing an annealed wafer wherein a silicon single crystal wafer having a diameter of 200 mm or more produced by the Czochralski (CZ) method is subjected to a high temperature heat treatment in an atmosphere of an argon gas, a hydrogen gas, or a mixture gas thereof at a temperature of 1100-1350° C. for 10-600 minutes, and before the high temperature heat treatmen, a pre-annealing is performed at a temperature less than the temperature of the high temperature heat treatment, so that the growth of slip dislocations is suppressed by growing oxide precipitates. Thereby, there is provided a method of producing an annealed wafer wherein the generation and growth of slip dislocations generated in a high temperature heat treatment are suppressed and the defect density in the wafer surface layer is lowered even in the case of a silicon single crystal wafer having a large diameter of 200 mm or more, and the annealed wafer.Type: ApplicationFiled: December 24, 2003Publication date: November 25, 2004Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya, Wei Feig Qu, Hiroshi Takeno, Ken Aihara
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Publication number: 20040003769Abstract: The present invention provides a method for producing a silicon wafer, which comprises growing a silicon single crystal ingot having a resistivity of 100 &OHgr;·cm or more and an initial interstitial oxygen concentration of 10 to 25 ppma and doped with nitrogen by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to a heat treatment so that a residual interstitial oxygen concentration in the wafer should become 8 ppma or less, and a method for producing a silicon wafer, which comprises growing a silicon single crystal ingot having a resistivity of 100 &OHgr;·cm or more and an initial interstitial oxygen concentration of 8 ppma or less and doped with nitrogen by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to a heat treatment to form an oxide precipitate layer in a bulk portion of the wafer, as well as silicon wafers produced by these production methods.Type: ApplicationFiled: March 18, 2003Publication date: January 8, 2004Inventors: Masaro Tamatsuka, Wei Feig Qu, Norihiro Kobayashi
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Publication number: 20020173173Abstract: The present invention provides an annealed wafer manufacturing method using a heat treatment method causing no change in resistivity of a wafer surface even when a silicon wafer having boron deposited on a surface thereof from an environment is subjected to heat treatment in an insert gas atmosphere and enabling the heat treatment in an ordinary diffusion furnace not requiring a sealed structure for increasing airtightness nor any specific facility such as explosion-proof facility. The present invention also provides an annealed wafer in which a boron concentration in the vicinity of a surface thereof is constant and crystal defects are annihilated.Type: ApplicationFiled: May 17, 2002Publication date: November 21, 2002Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya, Wei Feig Qu, Makoto Iida