Patents by Inventor Wei Fen Sueann LIM
Wei Fen Sueann LIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230361008Abstract: An electronic device includes a molded package structure and a conductive lead partially exposed outside the package structure, the package structure having lateral sides extending at an angle that is greater than 15 degrees and 25 degrees or less to facilitate mold cavity filling during package molding and mitigate mold voids in the electronic device. A method of fabricating an electronic device includes attaching a die to a lead frame, electrically coupling a conductive terminal of the die to a conductive lead and performing a molding process using a mold having cavity sidewalls with a draft angle greater than 15 degrees and 25 degrees or less to form a package structure that encloses the die and partially encloses the conductive lead.Type: ApplicationFiled: May 6, 2022Publication date: November 9, 2023Inventors: Wei Fen Sueann Lim, Jeevintharan A/L Sivasankaran, Khair Khaizal, Edwin Jin Keong Lim
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Patent number: 11791170Abstract: A method of making semiconductor packages includes providing a first lead frame having a first plurality of semiconductor dies arranged along a first longitudinal axis, each of the first plurality of semiconductor dies having a first number of metal contacts; providing a second lead frame having a second plurality of semiconductor dies arranged along a second longitudinal axis, each of the second plurality of semiconductor dies having a second number of metal contacts, the second number of metal contacts different than the first number of metal contacts; and covering the first plurality of semiconductor dies in a first mold using a common semiconductor die cavity; covering the second plurality of semiconductor dies in a second mold using the common semiconductor die cavity.Type: GrantFiled: April 22, 2021Date of Patent: October 17, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Anis Fauzi Bin Abdul Aziz, Chong Han Lim, Lee Han Meng@Eugene Lee, Wei Fen Sueann Lim
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Patent number: 11742263Abstract: A leadframe for electronic systems comprising a first sub-leadframe connected by links to a second sub-leadframe, the first and second sub-leadframe connected by tiebars to a frame; and each link having a neck suitable for bending the link, the necks arrayed in a line operable as the axis for bending the second sub-leadframe towards the first sub-leadframe with the necks operable as rotation pivots.Type: GrantFiled: November 19, 2020Date of Patent: August 29, 2023Assignee: Texas Instruments IncorporatedInventors: Lee Han Meng@ Eugene Lee, Anis Fauzi Bin Abdul Aziz, Wei Fen Sueann Lim
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Patent number: 11626350Abstract: A method includes forming a leadframe assembly to have a pair of opposing sides, and having semiconductor die receiving portions extending between the opposing sides. The method also includes placing semiconductor dies on the leadframe assembly in the die receiving portions. Each die has a row of leads on each of two opposing sides of the die and a longitudinal axis parallel to the rows of leads. The longitudinal axis of each die is orthogonal to the opposing sides of the leadframe assembly. The method further includes applying mold compound to the semiconductor dies. The method includes punching through the leadframe assembly between the opposing sides using a first tool having a first tool longitudinal axis parallel to longitudinal axes of the dies.Type: GrantFiled: April 3, 2020Date of Patent: April 11, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Chong Han Lim, Lee Han Meng@Eugene Lee, Anis Fauzi Bin Abdul Aziz, Wei Fen Sueann Lim, Siew Kee Lee
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Publication number: 20230069741Abstract: One example described herein includes an integrated circuit (IC) package. The IC package includes a semiconductor die comprising an IC and an IC package enclosure that substantially encloses the semiconductor die. The IC package also includes at least one conductive metal contact. Each of the at least one conductive metal contact is coupled to the semiconductor die and comprises a planar solder surface exterior to the IC package enclosure to which the respective at least one metal contact is soldered to an external conductive metal contact. The planar solder surface includes at least one solder surface feature.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: AMIRUL AFIQ BIN HUD, WEI FEN SUEANN LIM, ADI IRWAN BIN HERMAN
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Patent number: 11569152Abstract: An electronic device, a lead frame, and a method, including providing a lead frame with a Y-shaped feature having branch portions connected to a dam bar in a prospective gap in an equally spaced repeating lead pitch pattern, and a set of first leads extending parallel to one another along a first direction and spaced apart from one another along a second direction in lead locations of the repeating lead pitch pattern, attaching a semiconductor die to a die attach pad of the lead frame, attaching bond wires between bond pads of the semiconductor die, and the first leads, enclosing first portions of the first leads, the die attach pad, and a portion of the semiconductor die in a package structure, and performing a dam bar cut process that cuts through portions of the dam bar between the lead locations of the repeating lead pitch pattern.Type: GrantFiled: January 23, 2019Date of Patent: January 31, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Anis Fauzi Bin Abdul Aziz, Lee Han Meng@Eugene Lee, Wei Fen Sueann Lim, Siew Kee Lee
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Patent number: 11502045Abstract: An electronic device includes a semiconductor die, an enclosure, leads extending outwardly from the enclosure and electrically connected to the semiconductor die, and wherein the leads have a reduced cross-sectional area along a longitudinal length of the lead. The electronic device is designed to reduce the occurrence of crack formation between the leads and a printed circuit board.Type: GrantFiled: January 23, 2019Date of Patent: November 15, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Amirul Afiq bin Hud, Wei Fen Sueann Lim, Adi Irwan Herman
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Patent number: 11373940Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.Type: GrantFiled: September 22, 2020Date of Patent: June 28, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee Han Meng@Eugene Lee, Anis Fauzi bin Abdul Aziz, Wei Fen Sueann Lim
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Patent number: 11348806Abstract: A method of making Flat No-Lead Packages with plated lead surfaces exposed on lateral faces thereof. The method includes providing a plurality of Flat No-Lead Packages having severed, unplated lead surfaces exposed on lateral faces thereof and having plated lead surfaces exposed on bottom faces thereof. The method further includes batch electroplating the severed unplated lead surfaces of the plurality of Flat No-Lead Packages.Type: GrantFiled: December 23, 2014Date of Patent: May 31, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee Han Meng@ Eugene Lee, Shu Hui Ooi, Anis Fauzi Abdul Aziz, Wei Fen Sueann Lim
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Publication number: 20210242038Abstract: In accordance with at least one example of the disclosure, a system comprises a semiconductor package, comprising a first side surface having a first set of metal contacts extending therefrom; a second side surface having a second set of metal contacts extending therefrom; a top surface; a bottom surface; and an end surface meeting at least one of the first side surface, the second side surface, the top surface, and the bottom surface at a non-rounded edge.Type: ApplicationFiled: April 22, 2021Publication date: August 5, 2021Inventors: Anis Fauzi BIN ABDUL AZIZ, Chong Han LIM, Lee Han Meng@Eugene LEE, Wei Fen Sueann LIM
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Patent number: 11056462Abstract: A method of assembling a flip chip on a leadframe package. A locking dual leadframe (LDLF) includes a top metal frame portion including protruding features and a die pad and a bottom metal frame portion having apertures positioned lateral to the die pad. The protruding features and apertures are similarly sized and alignable. A flipped integrated circuit (IC) die having a bottomside and a topside including circuitry connected to bond pads having solder balls on the bond pads is mounted with its topside onto the top metal frame portion. The top metal frame portion is aligned to the bottom metal frame portion so that the protruding features are aligned to the apertures. The bottomside of the IC die is pressed with respect to a top surface of the bottom frame portion, wherein the protruding features penetrate into the apertures.Type: GrantFiled: July 10, 2017Date of Patent: July 6, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee Han Meng @ Eugene Lee, Wei Fen Sueann Lim, Anis Fauzi Bin Abdul Aziz
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Publication number: 20210202356Abstract: A method includes forming a leadframe assembly to have a pair of opposing sides, and having semiconductor die receiving portions extending between the opposing sides. The method also includes placing semiconductor dies on the leadframe assembly in the die receiving portions. Each die has a row of leads on each of two opposing sides of the die and a longitudinal axis parallel to the rows of leads. The longitudinal axis of each die is orthogonal to the opposing sides of the leadframe assembly. The method further includes applying mold compound to the semiconductor dies. The method includes punching through the leadframe assembly between the opposing sides using a first tool having a first tool longitudinal axis parallel to longitudinal axes of the dies.Type: ApplicationFiled: April 3, 2020Publication date: July 1, 2021Inventors: Chong Han LIM, Lee Han Meng@Eugene LEE, Anis Fauzi BIN ABDUL AZIZ, Wei Fen, Sueann LIM, Siew Kee LEE
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Publication number: 20210074613Abstract: A leadframe for electronic systems comprising a first sub-leadframe connected by links to a second sub-leadframe, the first and second sub-leadframe connected by tiebars to a frame; and each link having a neck suitable for bending the link, the necks arrayed in a line operable as the axis for bending the second sub-leadframe towards the first sub-leadframe with the necks operable as rotation pivots.Type: ApplicationFiled: November 19, 2020Publication date: March 11, 2021Inventors: Lee Han Meng@ Eugene Lee, Anis Fauzi Bin Abdul Aziz, Wei Fen, Sueann Lim
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Publication number: 20210043466Abstract: In accordance with at least one example of the disclosure, a system comprises a semiconductor package, comprising a first side surface having a first set of metal contacts extending therefrom; a second side surface having a second set of metal contacts extending therefrom; a top surface; a bottom surface; and an end surface meeting at least one of the first side surface, the second side surface, the top surface, and the bottom surface at a non-rounded edge.Type: ApplicationFiled: August 6, 2019Publication date: February 11, 2021Inventors: Anis Fauzi BIN ABDUL AZIZ, Chong Han LIM, Lee Han Meng@Eugene LEE, Wei Fen Sueann LIM
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Publication number: 20210005540Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.Type: ApplicationFiled: September 22, 2020Publication date: January 7, 2021Inventors: Lee Han Meng@Eugene Lee, Anis Fauzi bin Abdul Aziz, Wei Fen Sueann Lim
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Patent number: 10879154Abstract: A leadframe (100) for electronic systems comprising a first sub-leadframe (110) connected by links (150) to a second sub-leadframe (120), the first and second sub-leadframe connected by tiebars (111, 121) to a frame (130); and each link having a neck (151) suitable for bending the link, the necks arrayed in a line (170) operable as the axis for bending the second sub-leadframe towards the first sub-leadframe with the necks operable as rotation pivots.Type: GrantFiled: October 6, 2016Date of Patent: December 29, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee Han Meng@ Eugene Lee, Anis Fauzi Bin Abdul Aziz, Wei Fen Sueann Lim
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Patent number: 10784190Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.Type: GrantFiled: August 18, 2017Date of Patent: September 22, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee Han Meng@Eugene Lee, Anis Fauzi bin Abdul Aziz, Wei Fen Sueann Lim
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Publication number: 20200235042Abstract: An electronic device, a lead frame, and a method, including providing a lead frame with a Y-shaped feature having branch portions connected to a dam bar in a prospective gap in an equally spaced repeating lead pitch pattern, and a set of first leads extending parallel to one another along a first direction and spaced apart from one another along a second direction in lead locations of the repeating lead pitch pattern, attaching a semiconductor die to a die attach pad of the lead frame, attaching bond wires between bond pads of the semiconductor die, and the first leads, enclosing first portions of the first leads, the die attach pad, and a portion of the semiconductor die in a package structure, and performing a dam bar cut process that cuts through portions of the dam bar between the lead locations of the repeating lead pitch pattern.Type: ApplicationFiled: January 23, 2019Publication date: July 23, 2020Applicant: Texas Instruments IncorporatedInventors: Anis Fauzi Bin Abdul Aziz, Lee Han Meng@Eugene Lee, Wei Fen Sueann Lim, Siew Kee Lee
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Publication number: 20200235057Abstract: An electronic device includes a semiconductor die, an enclosure, leads extending outwardly from the enclosure and electrically connected to the semiconductor die, and wherein the leads have a reduced cross-sectional area along a longitudinal length of the lead. The electronic device is designed to reduce the occurrence of crack formation between the leads and a printed circuit board.Type: ApplicationFiled: January 23, 2019Publication date: July 23, 2020Applicant: Texas Instruments IncorporatedInventors: Amirul Afiq bin Hud, Wei Fen Sueann Lim, Adi Irwan Herman
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Publication number: 20200176365Abstract: In a described example, a packaged integrated circuit (IC) includes a lead frame with a lead and with an IC chip mount pad. A portion of the lead adjacent to the IC chip mount pad is mechanically deformed to form a lead lock. An integrated circuit chip is mounted on a first side of the IC chip mount pad; and the integrated circuit chip, the IC chip mount pad, and the portion are covered in molding compound.Type: ApplicationFiled: February 5, 2020Publication date: June 4, 2020Inventors: Bin Abdul Aziz Anis Fauzi, Wei Fen Sueann Lim, Lee Han Meng@Eugene Lee