Patents by Inventor Wei-Gang Chiu
Wei-Gang Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935935Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.Type: GrantFiled: November 11, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Min-Kun Dai, Wei-Gang Chiu, I-Cheng Chang, Cheng-Yi Wu, Han-Ting Tsai, Tsann Lin, Chung-Te Lin
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Publication number: 20240081081Abstract: A ferroelectric memory device and a semiconductor die are provided. The ferroelectric memory device includes a gate electrode; a channel layer, overlapped with the gate electrode; source/drain contacts, in contact with separate ends of the channel layer; a ferroelectric layer, lying between the gate electrode and the channel layer; and a first insertion layer, extending in between the ferroelectric layer and the channel layer, and comprising a metal carbonitride or a metal nitride.Type: ApplicationFiled: January 10, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Ling Lee, Chung-Te Lin, Han-Ting Tsai, Wei-Gang Chiu, Yen-Chieh Huang, Ming-Yi Yang
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Patent number: 11837667Abstract: A planar insulating spacer layer is formed over a substrate, and a vertical stack of a gate electrode, a gate dielectric layer, and a first semiconducting metal oxide layer may be formed thereabove. The first semiconducting metal oxide layer includes atoms of a first n-type dopant at a first average dopant concentration. A second semiconducting metal oxide layer is formed over the first semiconducting metal oxide layer. Portions of the second semiconducting metal oxide layer are doped with the second n-type dopant to provide a source-side n-doped region and a drain-side n-doped region that include atoms of the second n-type dopant at a second average dopant concentration that is greater than the first average dopant concentration. Various dopants may be introduced to enhance performance of the thin film transistor.Type: GrantFiled: June 29, 2022Date of Patent: December 5, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Min-Kun Dai, I-Cheng Chang, Cheng-Yi Wu, Han-Ting Tsai, Tsann Lin, Chung-Te Lin, Wei-Gang Chiu
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Publication number: 20230296701Abstract: In an embodiment, a device includes: a magnetoresistive random access memory cell including: a bottom electrode; a reference layer over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer including a first composition of magnesium and oxygen; a free layer over the tunnel barrier layer, the free layer having a lesser coercivity than the reference layer; a cap layer over the free layer, the cap layer including a second composition of magnesium and oxygen, the second composition of magnesium and oxygen having a greater atomic concentration of oxygen and a lesser atomic concentration of magnesium than the first composition of magnesium and oxygen; and a top electrode over the cap layer.Type: ApplicationFiled: May 26, 2023Publication date: September 21, 2023Inventors: Jui-Fen Chien, Wei-Gang Chiu, Tsann Lin
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Publication number: 20230261063Abstract: A semiconductor device includes a substrate, a gate electrode, a gate dielectric layer, a channel layer, a source electrode and a drain electrode. The gate electrode is disposed over the substrate. The gate dielectric layer is disposed over the gate electrode. The channel layer is disposed over the gate dielectric layer. The source electrode and the drain electrode are disposed over the channel layer and beside the gate electrode. In some embodiments, each of the source electrode and the drain electrode includes a glue layer and a metal pattern, and a thickness of the glue layer adjacent to a sidewall of the metal pattern is greater than a thickness of the glue layer adjacent to a bottom of the metal pattern.Type: ApplicationFiled: February 17, 2022Publication date: August 17, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Ling Lee, Wei-Gang Chiu, Han-Ting Tsai, Chung-Te Lin
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Patent number: 11698423Abstract: In an embodiment, a device includes: a magnetoresistive random access memory cell including: a bottom electrode; a reference layer over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer including a first composition of magnesium and oxygen; a free layer over the tunnel barrier layer, the free layer having a lesser coercivity than the reference layer; a cap layer over the free layer, the cap layer including a second composition of magnesium and oxygen, the second composition of magnesium and oxygen having a greater atomic concentration of oxygen and a lesser atomic concentration of magnesium than the first composition of magnesium and oxygen; and a top electrode over the cap layer.Type: GrantFiled: August 12, 2020Date of Patent: July 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jui-Fen Chien, Wei-Gang Chiu, Tsann Lin
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Publication number: 20230016126Abstract: One or more semiconductor processing tools may deposit one or more tantalum nitride layers on an upper surface of a copper interconnect and within a via. The one or more semiconductor processing tools may deposit an adhesion layer on an upper surface of the one or more tantalum nitride layers and within the via. The one or more semiconductor processing tools may deposit tungsten on an upper surface of the adhesion layer and within the via for via interconnection of the magnetic tunnel junction to the copper interconnect.Type: ApplicationFiled: July 16, 2021Publication date: January 19, 2023Inventors: Ya-Ling LEE, Wei-Gang CHIU, Ming-Hsing TSAI
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Publication number: 20220352333Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.Type: ApplicationFiled: November 11, 2021Publication date: November 3, 2022Inventors: Min-Kun DAI, Wei-Gang CHIU, I-Cheng CHANG, Cheng-Yi WU, Han-Ting TSAI, Tsann LIN, Chung-Te LIN
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Publication number: 20220336671Abstract: A planar insulating spacer layer is formed over a substrate, and a vertical stack of a gate electrode, a gate dielectric layer, and a first semiconducting metal oxide layer may be formed thereabove. The first semiconducting metal oxide layer includes atoms of a first n-type dopant at a first average dopant concentration. A second semiconducting metal oxide layer is formed over the first semiconducting metal oxide layer. Portions of the second semiconducting metal oxide layer are doped with the second n-type dopant to provide a source-side n-doped region and a drain-side n-doped region that include atoms of the second n-type dopant at a second average dopant concentration that is greater than the first average dopant concentration. Various dopants may be introduced to enhance performance of the thin film transistor.Type: ApplicationFiled: June 29, 2022Publication date: October 20, 2022Inventors: Min-Kun Dai, I-Cheng Chang, Cheng-Yi Wu, Han-Ting Tsai, Tsann Lin, Chung-Te Lin, Wei-Gang Chiu
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Publication number: 20220254930Abstract: A planar insulating spacer layer is formed over a substrate, and a vertical stack of a gate electrode, a gate dielectric layer, and a first semiconducting metal oxide layer may be formed thereabove. The first semiconducting metal oxide layer includes atoms of a first n-type dopant at a first average dopant concentration. A second semiconducting metal oxide layer is formed over the first semiconducting metal oxide layer. Portions of the second semiconducting metal oxide layer are doped with the second n-type dopant to provide a source-side n-doped region and a drain-side n-doped region that include atoms of the second n-type dopant at a second average dopant concentration that is greater than the first average dopant concentration. Various dopants may be introduced to enhance performance of the thin film transistor.Type: ApplicationFiled: February 11, 2021Publication date: August 11, 2022Inventors: Min-Kun DAI, I-Cheng CHANG, Cheng-Yi WU, Han-Ting TSAI, Tsann LIN, Chung-Te LIN, Wei-Gang CHIU
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Patent number: 11404586Abstract: A planar insulating spacer layer is formed over a substrate, and a vertical stack of a gate electrode, a gate dielectric layer, and a first semiconducting metal oxide layer may be formed thereabove. The first semiconducting metal oxide layer includes atoms of a first n-type dopant at a first average dopant concentration. A second semiconducting metal oxide layer is formed over the first semiconducting metal oxide layer. Portions of the second semiconducting metal oxide layer are doped with the second n-type dopant to provide a source-side n-doped region and a drain-side n-doped region that include atoms of the second n-type dopant at a second average dopant concentration that is greater than the first average dopant concentration. Various dopants may be introduced to enhance performance of the thin film transistor.Type: GrantFiled: February 11, 2021Date of Patent: August 2, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Min-Kun Dai, I-Cheng Chang, Cheng-Yi Wu, Han-Ting Tsai, Tsann Lin, Chung-Te Lin, Wei-Gang Chiu
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Publication number: 20220231036Abstract: An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. A ferroelectric layer formed according to the present teaching may be chlorine-free. Structures adjacent the ferroelectric layer are also formed with chlorine-free precursors. The absence of chlorine in the adjacent structures prevents diffusion of chlorine into the ferroelectric layer and prevents the formation of chlorine complexes at interfaces with the ferroelectric layer. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).Type: ApplicationFiled: April 8, 2022Publication date: July 21, 2022Inventors: Ya-Ling Lee, Wei-Gang Chiu, Yen-Chieh Huang, Han-Ting Tsai, Tsann Lin, Yu-Ming Lin, Chung-Te Lin
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Publication number: 20220050150Abstract: In an embodiment, a device includes: a magnetoresistive random access memory cell including: a bottom electrode; a reference layer over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer including a first composition of magnesium and oxygen; a free layer over the tunnel barrier layer, the free layer having a lesser coercivity than the reference layer; a cap layer over the free layer, the cap layer including a second composition of magnesium and oxygen, the second composition of magnesium and oxygen having a greater atomic concentration of oxygen and a lesser atomic concentration of magnesium than the first composition of magnesium and oxygen; and a top electrode over the cap layer.Type: ApplicationFiled: August 12, 2020Publication date: February 17, 2022Inventors: Jui-Fen Chien, Wei-Gang Chiu, Tsann Lin