Abstract: Embodiments of the present invention disclose an approach for data security and management. Specifically, the approach involves managing the analysis of sensitive data across multiple data centers. The system includes a data location repository that stores and updates information regarding the locations of sensitive data in data centers. When a request to access sensitive data from an analysis process is received, a specific data center where the data is stored is identified. The necessary components of the analysis process are transferred to that data center. The migrated analysis process is then executed using the locally stored sensitive data, without physically transferring the data. The generated analysis results are transferred back to the original data center where the analysis process originated.

Abstract: An early warning method for debris flow disaster in a small watershed, and a disaster reduction method for debris flows in a small watershed is disclosed. An early warning method for debris flow disaster in a small watershed is provided, in which parameters of a hydrological model are calibrated by rainfall, evaporation and runoff data of the watershed based on water balance of the watershed, and an early monitoring and warning scheme for debris flows, which takes water storage in the watershed as a core monitoring and evaluation indicator, is established. The GR4J hydrological model is improved by taking into account a watershed area, specific yield of an aquifer and several geological parameters, as well as an evapotranspiration effect of vegetation. A disaster reduction method by means of regulation of a drainage channel can provide a basis for mathematical model simulation studies of disaster reduction in small watersheds.

Abstract: A loop array mapping method of a shared balance operator is based on a reconfigurable cryptographic algorithm. The mapping graph is optimized by adopting a balance node operator mode, so that the mapping graph has a smallest iteration interval and a largest pipeline performance, thus solving a problem of poor pipeline performance of manual configuration and saving a great deal of human and mental labor, without adding the balance operator node manually by manual computing. In the present disclosure, a shared balance node operator solution is adopted to process a balance node of the multi-fan-out operator, so that computation resources are minimized and performance is maximized. The storage data unit SREG is used for data transfer and communication, which solves a problem that communication of data between loop bodies occupies more transfer operator resources, saves a lot of hardware resources and further improves pipeline performance.

Abstract: The present disclosure provides an interpreter of a reconfigurable cryptographic algorithm based on customized high-level C language, in the field of information security. The interpreter includes an input program of cryptographic algorithm customized language, a compilation optimization module, an intermediate file and data flow graph generation module, a mapping module and an array generation configuration code module. The disclosure provides an automatic mapping tool for the reconfigurable processor, which can take customized high-level C language as input, and the interpreter arranges and connects computing units like operators according to the input high-level C program, to complete the mapping of the whole computing function.

Abstract: The present disclosure discloses a flexible rehabilitation glove based on hybrid actuators. The flexible rehabilitation glove includes five hybrid actuators and an actuator control box, each hybrid actuator includes an actuator end mounting seat, a flexible actuator, a TPFE water pipe, a flexible actuator front section mounting seat, a flexible actuator air pipe, an air pipe connecting seat II, an SMA spring actuator, an air pipe connecting seat I and a cooling water pipe, the control box includes an air pump, a filter, a water pump and a water tank, a proportional valve and a control circuit board inside, and includes an actuator control box body, a control box cover, a main switch, a button and a voltage display outside, and the filter is connected to the air pump and the electrical proportional valve respectively.

Abstract: Embodiments of the present invention disclose an approach for data security and management. Specifically, the approach involves managing the analysis of sensitive data across multiple data centers. The system includes a data location repository that stores and updates information regarding the locations of sensitive data in data centers. When a request to access sensitive data from an analysis process is received, a specific data center where the data is stored is identified. The necessary components of the analysis process are transferred to that data center. The migrated analysis process is then executed using the locally stored sensitive data, without physically transferring the data. The generated analysis results are transferred back to the original data center where the analysis process originated.

Abstract: The present invention relates to a method, system and computer program product for task failover in an unstable environment, wherein the unstable environment includes a plurality of reclaimable nodes. According to the method, it is monitored if any node of the plurality of reclaimable nodes is to be reclaimed. Whether a task on any node of the plurality of reclaimable nodes is recoverable is determined. Responsive to the task being recoverable, data of the recoverable task is stored. Responsive to a node being reclaimed and the task on the reclaimed node being recoverable, at least one associated task of at least one associated node of the reclaimed node is notified to wait.

Abstract: The present disclosure discloses an information security application-oriented reconfigurable system chip compiler and an automatic compilation method. The method includes the following steps: firstly, inputting a source program of a cryptographic algorithm; then, executing a software compilation function syntax check of the source program, and when the check result is passed, performing compilation mapping using a compiler; next, executing the cryptographic algorithm by simulation running using a simulator, and generating a configuration code by a simulator array; and finally, guiding a hardware behavior operation using a binary configuration code file generated by the simulator. The reconfigurable system chip compiler includes a source program input module, a software compilation function verification module, a compilation mapping module, a simulation execution module, a configuration code generation module, and a hardware debugging module.

Abstract: Described herein are methods and a system for determining performance and providing a content score of translated content from an original source document or content. Quality and fitness of the original source content is checked, and translatability profile and natural language processing (NLP) profile is provided. The translatability profile and natural language processing (NLP) profile are used to provide a level of machine translation level to be performed on the original source document. The original source document or content is translated into a different language. The translated content is checked for quality, which is used along with user experience (UX) of the translated content to provide a content score of the translated content.

Abstract: A loop array mapping method of a shared balance operator is based on a reconfigurable cryptographic algorithm. The mapping graph is optimized by adopting a balance node operator mode, so that the mapping graph has a smallest iteration interval and a largest pipeline performance, thus solving a problem of poor pipeline performance of manual configuration and saving a great deal of human and mental labor, without adding the balance operator node manually by manual computing. In the present disclosure, a shared balance node operator solution is adopted to process a balance node of the multi-fan-out operator, so that computation resources are minimized and performance is maximized. The storage data unit SREG is used for data transfer and communication, which solves a problem that communication of data between loop bodies occupies more transfer operator resources, saves a lot of hardware resources and further improves pipeline performance.

Abstract: A present invention embodiment requests resources for a set of tasks from different resource providers. The set of tasks includes first tasks and second tasks of longer duration than the first tasks. The resources are revocable by the different resource providers based on processing demand. Performance of the first tasks is initiated on the resources, and stable resources are identified based on revocation of the resources during performance of the first tasks. Performance of the second tasks are initiated on the identified stable resources. Requests for the resources to the different resource providers are adjusted based on resource provider information collected in response to completion of the set of tasks.

Abstract: The present disclosure provides an interpreter of a reconfigurable cryptographic algorithm based on customized high-level C language, in the field of information security. The interpreter includes an input program of cryptographic algorithm customized language, a compilation optimization module, an intermediate file and data flow graph generation module, a mapping module and an array generation configuration code module. The disclosure provides an automatic mapping tool for the reconfigurable processor, which can take customized high-level C language as input, and the interpreter arranges and connects computing units like operators according to the input high-level C program, to complete the mapping of the whole computing function.

Abstract: A block of data intended for a set of receiving computer systems comprising a first system and a second system is divided into a set of equal-size portions. A first portion of the set of portions is transmitted from a first file server storing the block of data to the first system. The first portion is relayed from the first file server to a second file server concurrently with the transmitting. The first portion of the set of portions is transmitted from the second file server to the second system.

Abstract: An intelligent trash can includes a closing and packing mechanism for automatic closing of a garbage bag. The closing and packing mechanism include a pair of first pressing rods and a second pressing rod. The pair of first pressing rods are configured for being synchronously approached or synchronously moved away under the driving of a first belt transmission unit. The second pressing rod is perpendicular to the pair of first pressing rods. The second pressing rod is configured to perform linear reciprocating motion along a length direction of the pair of first pressing rods under the driving of the second belt transmission unit.

Abstract: The present invention relates to a method, system and computer program product for task failover in an unstable environment, wherein the unstable environment includes a plurality of reclaimable nodes. According to the method, it is monitored if any node of the plurality of reclaimable nodes is to be reclaimed. Whether a task on any node of the plurality of reclaimable nodes is recoverable is determined. Responsive to the task being recoverable, data of the recoverable task is stored. Responsive to a node being reclaimed and the task on the reclaimed node being recoverable, at least one associated task of at least one associated node of the reclaimed node is notified to wait.

Abstract: The present disclosure discloses an information security application-oriented reconfigurable system chip compiler and an automatic compilation method. The method includes the following steps: firstly, inputting a source program of a cryptographic algorithm; then, executing a software compilation function syntax check of the source program, and when the check result is passed, performing compilation mapping using a compiler; next, executing the cryptographic algorithm by simulation running using a simulator, and generating a configuration code by a simulator array; and finally, guiding a hardware behavior operation using a binary configuration code file generated by the simulator. The reconfigurable system chip compiler includes a source program input module, a software compilation function verification module, a compilation mapping module, a simulation execution module, a configuration code generation module, and a hardware debugging module.

Abstract: A block of data intended for a set of receiving computer systems comprising a first system and a second system is divided into a set of equal-size portions. A first portion of the set of portions is transmitted from a first file server storing the block of data to the first system. The first portion is relayed from the first file server to a second file server concurrently with the transmitting. The first portion of the set of portions is transmitted from the second file server to the second system.

Abstract: For resource management for a parent child workload, a processor organizes a plurality of processes into a plurality of process groups. Each process group includes a given parent process and all child processes of the given parent process. Each process group has a process level. The processor further calculates a process cost for each process group and assigns a process priority to each process group based on the process cost for the process group. The processor iteratively assigns computing resources to subgroups of a given process group with a highest process priority at a given process level.

Abstract: The present invention relates to the field of analog integrated circuits, and provides a multiply-accumulate calculation method and circuit suitable for a neural network, which realizes large-scale multiply-accumulate calculation of the neural network with low power consumption and high speed. The multiply-accumulate calculation circuit comprises a multiplication calculation circuit array and an accumulation calculation circuit. The multiplication calculation circuit array is composed of M groups of multiplication calculation circuits. Each group of multiplication calculation circuits is composed of one multiplication array unit and eight selection-shift units. The order of the multiplication array unit is quantized in real time by using on-chip training to provide a shared input for the selection-shift units, achieving increased operating rate and reduced power consumption.