Patents by Inventor Wei-Han Fan

Wei-Han Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230378304
    Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.
    Type: Application
    Filed: August 2, 2023
    Publication date: November 23, 2023
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Yee-Chia Yeo, Wei Hao Lu
  • Publication number: 20230134971
    Abstract: Source/drain epitaxial features and methods for fabricating such are disclosed herein. An exemplary method includes receiving a substrate including a n-type region and a p-type region, forming a stack of semiconductor layers over the substrate, the stack of semiconductor layers including interleaving first material layers and second material layers, and performing an etch process to form a first source/drain recess in the n-type region and a second source/drain recess in the p-type region. The method further includes depositing a metal-containing layer over the stack of semiconductor layers, including within the first source/drain recess and the second source/drain recess, removing the metal-containing layer from the n-type region, and forming an n-type epitaxial source/drain feature in the first source/drain recess. The method further includes removing the metal-containing layer from the p-type region and forming a p-type epitaxial source/drain structure in the second source/drain recess.
    Type: Application
    Filed: July 26, 2022
    Publication date: May 4, 2023
    Inventors: Wei-Han Fan, Chia-Pin Lin, Wei-Yang Lee, Tzu-Hua Chiu, I-Hsieh Wong, Alex Lee
  • Publication number: 20230065318
    Abstract: A method of forming a semiconductor including forming a source/drain feature adjacent to a semiconductor layer stack disposed over a substrate. The method further includes forming a dummy fin adjacent to the source/drain feature and adjacent to the semiconductor layer stack. The method further includes performing an etching process from a backside of the substrate to remove a first portion of the dummy fin adjacent to the source/drain feature, thereby forming a first trench in the dummy fin, where the first trench extends from the dummy fin to the source/drain feature. The method further includes forming a first dielectric layer in the first trench and replacing a second portion of the dummy fin with a source/drain contact.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Wei-Han Fan, Wei-Yang Lee, Tzu-Hua Chiu, Chia-Pin Lin
  • Publication number: 20230052084
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, and a first inner spacer layer interposing the gate stack and the source/drain feature and interposing the first nanostructure and the second nanostructure. A dopant in the source/drain feature has a first concentration at an interface between the first inner spacer layer and the source/drain feature and a second concentration at a first distance away from the interface. The first concentration is higher than the second concentration.
    Type: Application
    Filed: August 12, 2021
    Publication date: February 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Hao CHENG, Wei-Yang LEE, Tzu-Hua CHIU, Wei-Han FAN, Po-Yu LIN, Chia-Pin LIN
  • Publication number: 20230018266
    Abstract: A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, and a source/drain feature disposed over the substrate and coupled to the vertical stack of channel members. The source/drain feature is spaced apart from a sidewall of the gate structure by an air gap and a dielectric layer, and the air gap extends into the source/drain feature.
    Type: Application
    Filed: May 5, 2022
    Publication date: January 19, 2023
    Inventors: Wei-Han Fan, Chia-Pin Lin, Wei-Yang Lee, Tzu-Hua Chiu, Kuan-Hao Cheng, Po Shao Lin
  • Publication number: 20230017036
    Abstract: A method of fabricating a device includes providing a fin having a stack of epitaxial layers including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. A source/drain etch process is performed to remove portions of the stack of epitaxial layers in source/drain regions to form trenches that expose lateral surfaces of the stack of epitaxial layers. A dummy layer recess process is performed to laterally etch the plurality of dummy layers to form recesses along sidewalls of the trenches. An inner spacer material is deposited along sidewalls of the trenches and within the recesses. An inner spacer etch-back process is performed to remove the inner spacer material from the sidewalls of the trenches and to remove a portion of the inner spacer material from within the recesses to form inner spacers having a dish-like region along lateral surfaces of the inner spacers.
    Type: Application
    Filed: May 4, 2022
    Publication date: January 19, 2023
    Inventors: Wei-Han FAN, Chia-Pin LIN, Wei-Yang LEE, Tzu-Hua CHIU, Kuan-Hao CHENG, Po Shao LIN
  • Publication number: 20230019386
    Abstract: Semiconductor devices and methods are provided. In an embodiment, a semiconductor device includes first nanostructures directly over a first portion of a substrate and second nanostructures directly over a second portion of the substrate, n-type source/drain features coupled to the first nanostructures and p-type source/drain features coupled to the second nanostructures, and an isolation structure disposed between the first portion of the substrate and the second portion of the substrate. The isolation structure includes a first smiling region in direct contact with the first portion of the substrate and having a first height. The isolation structure also includes a second smiling region in direct contact with the second portion of the substrate and having a second height, the first height is greater than the second height.
    Type: Application
    Filed: May 24, 2022
    Publication date: January 19, 2023
    Inventors: Kuan-Hao Cheng, Chia-Pin Lin, Wei-Yang Lee, Tzu-Hua Chiu, Wei-Han Fan, Po-Yu Lin
  • Publication number: 20230018480
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a gate stack over a top portion of the fin. The semiconductor device structure includes a first nanostructure over the fin and passing through the gate stack. The semiconductor device structure includes a second nanostructure over the first nanostructure and passing through the gate stack. The first nanostructure is thicker than the second nanostructure. The semiconductor device structure includes a stressor structure over the fin and connected to the first nanostructure and the second nanostructure.
    Type: Application
    Filed: July 16, 2021
    Publication date: January 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Hao CHENG, Wei-Yang LEE, Tzu-Hua CHIU, Wei-Han FAN, Po-Yu LIN, Chia-Pin LIN
  • Publication number: 20220328648
    Abstract: A semiconductor device includes a base portion on a semiconductor substrate, a channel layer vertically above the base portion and extending parallel to a top surface of the semiconductor substrate, a gate portion between the channel layer and the base portion, a source/drain feature connected to the channel layer, an inner spacer between the source/drain feature and the gate portion, and an air gap between the source/drain feature and the semiconductor substrate. Moreover, a bottom surface of the source/drain feature is exposed in the air gap.
    Type: Application
    Filed: September 2, 2021
    Publication date: October 13, 2022
    Inventors: I-Hsieh Wong, Alex Lee, Wei-Han Fan, Tzu-Hua Chiu, Wei-Yang Lee, Chia-Pin Lin
  • Publication number: 20220320276
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.
    Type: Application
    Filed: August 5, 2021
    Publication date: October 6, 2022
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
  • Publication number: 20220320307
    Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.
    Type: Application
    Filed: September 1, 2021
    Publication date: October 6, 2022
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Yee-Chia Yeo, Wei Hao Lu
  • Patent number: 10868149
    Abstract: A method includes providing a structure having a substrate and a fin extending from the substrate, wherein the fin includes a first semiconductor material and has a source region, a channel region, and a drain region for a transistor; forming a gate stack over the channel region; performing a surface treatment to the fin in the source and drain regions, thereby converting an outer portion of the fin in the source and drain regions into a different material other than the first semiconductor material; etching the converted outer portion of the fin in the source and drain regions, thereby reducing a width of the fin in the source and drain regions; and depositing an epitaxial layer over the fin in the source and drain regions.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Han Fan, Wei-Yuan Lu, Yu-Lin Yang, Chun-Hsiang Fan, Sai-Hooi Yeong
  • Publication number: 20200044062
    Abstract: A method includes providing a structure having a substrate and a fin extending from the substrate, wherein the fin includes a first semiconductor material and has a source region, a channel region, and a drain region for a transistor; forming a gate stack over the channel region; performing a surface treatment to the fin in the source and drain regions, thereby converting an outer portion of the fin in the source and drain regions into a different material other than the first semiconductor material; etching the converted outer portion of the fin in the source and drain regions, thereby reducing a width of the fin in the source and drain regions; and depositing an epitaxial layer over the fin in the source and drain regions.
    Type: Application
    Filed: October 14, 2019
    Publication date: February 6, 2020
    Inventors: Wei-Han Fan, Wei-Yuan Lu, Yu-Lin Yang, Chun-Hsiang Fan, Sai-Hooi Yeong
  • Patent number: 10446669
    Abstract: A method includes providing a structure having a substrate and a fin extending from the substrate, wherein the fin includes a first semiconductor material and has a source region, a channel region, and a drain region for a transistor; forming a gate stack over the channel region; performing a surface treatment to the fin in the source and drain regions, thereby converting an outer portion of the fin in the source and drain regions into a different material other than the first semiconductor material; etching the converted outer portion of the fin in the source and drain regions, thereby reducing a width of the fin in the source and drain regions; and depositing an epitaxial layer over the fin in the source and drain regions.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 15, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Han Fan, Wei-Yuan Lu, Yu-Lin Yang, Chun-Hsiang Fan, Sai-Hooi Yeong
  • Publication number: 20190165139
    Abstract: A method includes providing a structure having a substrate and a fin extending from the substrate, wherein the fin includes a first semiconductor material and has a source region, a channel region, and a drain region for a transistor; forming a gate stack over the channel region; performing a surface treatment to the fin in the source and drain regions, thereby converting an outer portion of the fin in the source and drain regions into a different material other than the first semiconductor material; etching the converted outer portion of the fin in the source and drain regions, thereby reducing a width of the fin in the source and drain regions; and depositing an epitaxial layer over the fin in the source and drain regions.
    Type: Application
    Filed: April 27, 2018
    Publication date: May 30, 2019
    Inventors: Wei-Han Fan, Wei-Yuan Lu, Yu-Lin Yang, Chun-Hsiang Fan, Sai-Hooi Yeong
  • Publication number: 20190123198
    Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 25, 2019
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Patent number: 10164093
    Abstract: An exemplary method includes forming a dummy gate structure over a substrate and forming a set of spacers adjacent to the dummy gate structure. The set of spacers includes spacer liners disposed on sidewalls of the dummy gate structure and main spacers disposed on the spacer liners. The spacer liners include silicon and carbon. The method further includes forming source/drain epitaxy regions over the substrate. The source/drain epitaxy regions are disposed adjacent to the set of spacers, such that the dummy gate structure is disposed between the source/drain epitaxy regions. The method further includes removing the main spacers after forming the source/drain epitaxy regions. The method further includes replacing the dummy gate structure with a gate structure, where the replacing includes removing the dummy gate structure to form a trench defined by the spacers liners, such that the gate structure is formed in the trench.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Patent number: 9698057
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Feng Nieh, Ming-Huan Tsai, Wei-Han Fan, Yimin Huang, Chun-Fai Cheng, Han-Ting Tsai, Chii-Ming Wu
  • Publication number: 20170186867
    Abstract: An exemplary method includes forming a dummy gate structure over a substrate and forming a set of spacers adjacent to the dummy gate structure. The set of spacers includes spacer liners disposed on sidewalls of the dummy gate structure and main spacers disposed on the spacer liners. The spacer liners include silicon and carbon. The method further includes forming source/drain epitaxy regions over the substrate. The source/drain epitaxy regions are disposed adjacent to the set of spacers, such that the dummy gate structure is disposed between the source/drain epitaxy regions. The method further includes removing the main spacers after forming the source/drain epitaxy regions. The method further includes replacing the dummy gate structure with a gate structure, where the replacing includes removing the dummy gate structure to form a trench defined by the spacers liners, such that the gate structure is formed in the trench.
    Type: Application
    Filed: March 13, 2017
    Publication date: June 29, 2017
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Patent number: D1016074
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: February 27, 2024
    Assignee: GETAC TECHNOLOGY CORPORATION
    Inventors: Sheng-Han Fan, Wei-Sen Lu