Patents by Inventor Wei-Hao Chen

Wei-Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240421004
    Abstract: In an embodiment, a method includes: forming a plurality of fins over a substrate, the plurality of fins comprising: a first semiconductor fin adjacent to an isolation region; and a dielectric fin embedded in the isolation region; depositing a silicon layer over a first surface of the first semiconductor fin, a second surface of the dielectric fin, and a third surface of the isolation region; forming an oxide layer over the silicon layer; removing a portion of the oxide layer and the silicon layer to expose the second surface of the dielectric fin; forming a dummy gate over a remaining portion of the oxide layer and between the plurality of fins; forming a first epitaxial region in the first semiconductor fin; and replacing the dummy gate with a gate structure.
    Type: Application
    Filed: June 13, 2023
    Publication date: December 19, 2024
    Inventors: Wei-Hao Wu, Ying Tsung Chen
  • Publication number: 20240408177
    Abstract: The present disclosure provides IL-10 muteins and use of IL-10 muteins in fusion proteins. The IL-10 mutein or the fusion protein comprise one or more substitution on amino acids in position 104, position 107, and a combination thereof, relative to amino acids of wild-type IL-10. Advantageously, the IL-10 mutein or the fusion protein thereof are provided with reduced aggregation potency during purification and extended half-life.
    Type: Application
    Filed: October 6, 2022
    Publication date: December 12, 2024
    Inventors: Hung-Kai CHEN, Po-Hao Chang, Wei Huang, Jing-Yi Huang, Pandelakis Andreas KONI, Tsung-Hao CHANG, Shih-Rang YANG, Yin-Ping WANG
  • Patent number: 12167526
    Abstract: An extreme ultraviolet (EUV) photolithography system generates EUV light by irradiating droplets with a laser. The system includes a droplet generator with a nozzle and a piezoelectric structure coupled to the nozzle. The generator outputs groups of droplets. A control system applies a voltage waveform to the piezoelectric structure while the nozzle outputs the group of droplets. The waveform causes the droplets of the group to have a spread of velocities that results in the droplets coalescing into a single droplet prior to being irradiated by the laser.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Kuang Sun, Cheng-Hao Lai, Yu-Huan Chen, Wei-Shin Cheng, Ming-Hsun Tsai, Hsin-Feng Chen, Chiao-Hua Cheng, Cheng-Hsuan Wu, Yu-Fa Lo, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
  • Publication number: 20240405053
    Abstract: Some implementations described herein include a complementary metal oxide semiconductor image sensor device and techniques to form the complementary metal oxide semiconductor image sensor device. The complementary metal oxide semiconductor image sensor device includes a includes a first array of photodiodes stacked over a second array of photodiodes. A polarization structure is between the first array of photodiodes and the second array of photodiodes. Signaling generated by the first array of photodiodes (e.g., signaling corresponding to unpolarized light waves) may be multiplexed with signaling generated by the second array of photodiodes (e.g., signaling corresponding to polarized light waves). The complementary metal oxide semiconductor image sensor device further includes a filter structure that filters visible light waves and near infrared light waves amongst the first array of photodiodes and the second array of photodiodes.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 5, 2024
    Inventors: Chun-Liang LU, Wei-Lin CHEN, Chun-Hao CHOU, Kuo-Cheng LEE
  • Publication number: 20240402423
    Abstract: A quantum memory device includes: a waveguide configured to spatially confine paths of photons therein; a memory cell that includes a micro-ring resonator (MRR), a frequency tuner, and a quantum memory material portion, wherein the MRR includes a first segment that is parallel to a segment of the waveguide, wherein the frequency tuner is configured to modulate a photon resonance frequency in the MRR by modifying an effective refractive index within, or around, a second segment of the MRR, and wherein the quantum memory material portion includes a quantum memory material having a ground state and an excitation state that stores photons therein and located within or on a third segment of the MRR; and a control circuit configured to modulate the photon resonance wavelength in the MRR during a first step of a photon capture operation to match a predefined wavelength, and to generate captured photons in the MRR.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 5, 2024
    Inventors: Chung-Hao Tsai, Ching-Ho Chin, Wei-Ting Chen, Chuei-Tang Wang, Chen-Hua Yu
  • Publication number: 20240404871
    Abstract: Methods for forming a dielectric isolation region between two active regions are disclosed herein. A mandrel is formed on a substrate, then etched to form a trench. Spacers are formed on the sidewalls of the mandrel. The mandrel is removed, and the substrate is etched to form fins extending in a first direction in the two active regions, and of fins extending in a second direction. A mask is formed that exposes the substrate between the fins extending in the second direction. The substrate is etched to form a trench. The trench is filled with a dielectric material up to the top of the fins to form the dielectric isolation region. The methods provide better depth control during etching between the two active regions, and also permit the trench to extend deeper into the substrate due to reduced depth/width ratios during the etching steps.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventors: Wei Che Tsai, Yuan Tsung Tsai, Hsin-Yi Tsai, Ying Ming Wang, Hsien Hua Tseng, Shih-Hao Chen
  • Publication number: 20240395871
    Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Wei-Ting Chien, Wen-Yen Chen, Li-Ting Wang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang
  • Patent number: 12154949
    Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Ting Chien, Wen-Yen Chen, Li-Ting Wang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang
  • Publication number: 20240387265
    Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.
    Type: Application
    Filed: July 28, 2024
    Publication date: November 21, 2024
    Inventors: Pin-Wen Chen, Chang-Ting Chung, Yi-Hsiang Chao, Yu-Ting Wen, Kai-Chieh Yang, Yu-Chen Ko, Peng-Hao Hsu, Ya-Yi Cheng, Min-Hsiu Hung, Chun-Hsien Huang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20240387180
    Abstract: The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Meng-Han Chou, Kuan-Yu Yeh, Wei-Yip Loh, Hung-Hsu Chen, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240386976
    Abstract: An array of memory cells includes a resistive component disposed in thermal communication with a group of memory cells in the array of memory cells. A capacitor and a circuit to cause discharge of the capacitor via the resistive component induces thermal anneal of the group of memory cells. A charge pump and a circuit to enable the charge pump to precharge the capacitor can be used. The charge pump, the capacitor and the array of memory cells can be disposed on a single integrated circuit. The group of memory cells can be arranged in a 3D stack having multiple levels, and the resistive component can be “snaked” through the stack. The thermal anneal can be executing in timing coordination with erase operations in flash memory.
    Type: Application
    Filed: May 18, 2023
    Publication date: November 21, 2024
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hang-Ting LUE, Teng-Hao YEH, Wei-Chen CHEN
  • Publication number: 20240387257
    Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Pin-Hsuan Yeh, Wei-Chin Lee, Hsien-Ming Lee, Chien-Hao Chen, Chi On Chui
  • Publication number: 20240387194
    Abstract: A passivation layer and conductive via are provided, wherein the transmittance of an imaging energy is increased within the material of the passivation layer. The increase in transmittance allows for a greater cross-linking that helps to increase control over the contours of openings formed within the passivation layer. Once the openings are formed, the conductive vias can be formed within the openings.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Wei-Chih Chen, Yu-Hsiang Hu, Hung-Jui Kuo, Sih-Hao Liao
  • Publication number: 20240387574
    Abstract: Implementations described herein reduce electron-hole pair generation due to silicon dangling bonds in pixel sensors. In some implementations, the silicon dangling bonds in a pixel sensor may be passivated by silicon-fluorine (Si—F) bonding in various portions of the pixel sensor such as a transfer gate contact via or a shallow trench isolation region, among other examples. The silicon-fluorine bonds are formed by fluorine implantation and/or another type of semiconductor processing operation. In some implementations, the silicon-fluorine bonds are formed as part of a cleaning operation using fluorine (F) such that the fluorine may bond with the silicon of the pixel sensor. Additionally, or alternatively, the silicon-fluorine bonds are formed as part of a doping operation in which boron (B) and/or another p-type doping element is used with fluorine such that the fluorine may bond with the silicon of the pixel sensor.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Wei-Lin CHEN, Chun-Hao CHOU, Kuo-Cheng LEE
  • Publication number: 20240387599
    Abstract: An array of nanoscale structures over photodiodes of a pixel array improves quantum efficiency (QE) for shorter wavelengths of light, such as green light and blue light. The nanoscale structures may be used without high absorption (HA) structures (e.g., when the pixel array is configured only for visible light) or may at least partially surround HA structures (e.g., when the pixel array is configured both for visible light and near infrared light). Additionally, the array of nanoscale structures may be formed using photolithography such that the nanoscale structures are approximately spaced at regular intervals. Therefore, QE for the pixel array is improved more than if the array of nanoscale structures were to be formed using a random (or quasi-random) process.
    Type: Application
    Filed: May 17, 2023
    Publication date: November 21, 2024
    Inventors: Wei-Lin CHEN, Chun-Hao CHOU, Kun-Hui LIN, Kuo-Cheng LEE
  • Publication number: 20240379738
    Abstract: A package structure and a formation method are provided. The method includes forming a capacitor element over a first chip structure and forming a dielectric layer over the capacitor element. The method also includes forming a conductive bonding structure in the dielectric layer. A top surface of the conductive bonding structure is substantially coplanar with a top surface of the dielectric layer. The conductive bonding structure penetrates through the capacitor element and is electrically connected to the capacitor element. The method further includes bonding a second chip structure to the dielectric layer and the conductive bonding structure through dielectric-to-dielectric bonding and metal-to-metal bonding.
    Type: Application
    Filed: May 10, 2023
    Publication date: November 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Ting CHEN, Chung-Hao TSAI, Chen-Hua YU, Chuei-Tang WANG
  • Publication number: 20240376303
    Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Photoresist layer is selectively exposed to radiation, and selectively exposed photoresist layer developed. Photoresist composition includes photoactive compound, crosslinker, copolymer.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-hao CHEN, Wei-Han LAI, Ching-Yu CHANG
  • Publication number: 20240379611
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first wafer including a first metal structure within a body of the first wafer. The semiconductor structure also includes a second wafer including a second metal structure within a body of the second wafer, where the first wafer is coupled to the second wafer at an interface. The semiconductor structure further includes a metal bonding structure coupled to the first metal structure and the second metal structure and extending through the interface.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Chun-Liang LU, Wei-Lin CHEN, Chun-Hao CHOU, Kuo-Cheng LEE
  • Patent number: 12140159
    Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.
    Type: Grant
    Filed: January 9, 2024
    Date of Patent: November 12, 2024
    Assignee: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Chun-Chieh Wang, Shu-Hao Kuo
  • Publication number: 20240371840
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu