Abstract: An array of nanoscale structures over photodiodes of a pixel array improves quantum efficiency (QE) for shorter wavelengths of light, such as green light and blue light. The nanoscale structures may be used without high absorption (HA) structures (e.g., when the pixel array is configured only for visible light) or may at least partially surround HA structures (e.g., when the pixel array is configured both for visible light and near infrared light). Additionally, the array of nanoscale structures may be formed using photolithography such that the nanoscale structures are approximately spaced at regular intervals. Therefore, QE for the pixel array is improved more than if the array of nanoscale structures were to be formed using a random (or quasi-random) process.

Abstract: Implementations described herein reduce electron-hole pair generation due to silicon dangling bonds in pixel sensors. In some implementations, the silicon dangling bonds in a pixel sensor may be passivated by silicon-fluorine (Si—F) bonding in various portions of the pixel sensor such as a transfer gate contact via or a shallow trench isolation region, among other examples. The silicon-fluorine bonds are formed by fluorine implantation and/or another type of semiconductor processing operation. In some implementations, the silicon-fluorine bonds are formed as part of a cleaning operation using fluorine (F) such that the fluorine may bond with the silicon of the pixel sensor. Additionally, or alternatively, the silicon-fluorine bonds are formed as part of a doping operation in which boron (B) and/or another p-type doping element is used with fluorine such that the fluorine may bond with the silicon of the pixel sensor.

Abstract: A passivation layer and conductive via are provided, wherein the transmittance of an imaging energy is increased within the material of the passivation layer. The increase in transmittance allows for a greater cross-linking that helps to increase control over the contours of openings formed within the passivation layer. Once the openings are formed, the conductive vias can be formed within the openings.

Abstract: The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

Abstract: An array of memory cells includes a resistive component disposed in thermal communication with a group of memory cells in the array of memory cells. A capacitor and a circuit to cause discharge of the capacitor via the resistive component induces thermal anneal of the group of memory cells. A charge pump and a circuit to enable the charge pump to precharge the capacitor can be used. The charge pump, the capacitor and the array of memory cells can be disposed on a single integrated circuit. The group of memory cells can be arranged in a 3D stack having multiple levels, and the resistive component can be “snaked” through the stack. The thermal anneal can be executing in timing coordination with erase operations in flash memory.

Abstract: A package structure and a formation method are provided. The method includes forming a capacitor element over a first chip structure and forming a dielectric layer over the capacitor element. The method also includes forming a conductive bonding structure in the dielectric layer. A top surface of the conductive bonding structure is substantially coplanar with a top surface of the dielectric layer. The conductive bonding structure penetrates through the capacitor element and is electrically connected to the capacitor element. The method further includes bonding a second chip structure to the dielectric layer and the conductive bonding structure through dielectric-to-dielectric bonding and metal-to-metal bonding.

Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Photoresist layer is selectively exposed to radiation, and selectively exposed photoresist layer developed. Photoresist composition includes photoactive compound, crosslinker, copolymer.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first wafer including a first metal structure within a body of the first wafer. The semiconductor structure also includes a second wafer including a second metal structure within a body of the second wafer, where the first wafer is coupled to the second wafer at an interface. The semiconductor structure further includes a metal bonding structure coupled to the first metal structure and the second metal structure and extending through the interface.

Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Photoresist layer is selectively exposed to radiation, and selectively exposed photoresist layer developed. Photoresist composition includes photoactive compound, crosslinker, copolymer.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having an active region as the substrate includes a medium-voltage (MV) region and a low-voltage (LV) region, forming a first divot adjacent to one side of the active region, forming a second divot adjacent to another side of the active region, forming a first liner in the first divot and the second divot and on the substrate of the MV region and LV region, forming a second liner on the first liner, and then removing the second liner, the first liner, and the substrate on the LV region for forming a fin-shaped structure.

Abstract: The present disclosure is directed to a modularized vessel droplet generator assembly (MGDVA) including a droplet generator assembly (DGA). Under a normal operation, the liquid fuel moves along an operation pathway extending through the DGA to eject or discharge the liquid fuel (e.g., liquid tin) from a nozzle of the DGA into a vacuum chamber. The liquid fuel in the vacuum chamber is then exposed to a laser generating an extreme ultra-violet (EUV) light. Under a service operation, the operation pathway is closed and a service pathway extending through the DGA is opened. A gas is introduced into the service pathway forming a gas-liquid interface between the gas and the liquid fuel. The gas-liquid interface is driven to an isolation valve directly adjacent to the DGA. In other words, the gas pushes back the liquid fuel to the isolation valve. Once the gas-liquid interface reaches the isolation valve, the isolation valve is closed isolating the DGA from the liquid fuel.

Abstract: A method of inspecting an extreme ultraviolet (EUV) radiation source includes, in an idle mode, inserting a borescope mounted on a fixture through a first opening into a chamber of the EUV radiation source. The borescope includes a connection cable attached at a first end to a camera. The EUV radiation source includes an excitation laser that generates a light beam that is configured to focus onto tin droplets to generate EUV radiation inside the chamber of the EUV radiation source. The method further includes extending the extendible section, in a direction toward the second opening of the EUV radiation source, to move the camera beyond the blocking shield, and acquiring one or more images from a region beyond the blocking shield. The method also includes analyzing the one or more acquired images to determine an amount of tin debris deposited inside the chamber of the EUV radiation source.

Abstract: The present disclosure is directed to a modularized vessel droplet generator assembly (MGDVA) including a droplet generator assembly (DGA). Under a normal operation, the liquid fuel moves along an operation pathway extending through the DGA to eject or discharge the liquid fuel (e.g., liquid tin) from a nozzle of the DGA into a vacuum chamber. The liquid fuel in the vacuum chamber is then exposed to a laser generating an extreme ultra-violet (EUV) light. Under a service operation, the operation pathway is closed and a service pathway extending through the DGA is opened. A gas is introduced into the service pathway forming a gas-liquid interface between the gas and the liquid fuel. The gas-liquid interface is driven to an isolation valve directly adjacent to the DGA. In other words, the gas pushes back the liquid fuel to the isolation valve. Once the gas-liquid interface reaches the isolation valve, the isolation valve is closed isolating the DGA from the liquid fuel.

Abstract: A non-volatile memory device and its manufacturing method are provided. The non-volatile memory device includes a substrate and a plurality of first floating gates and a plurality of second floating gates formed on the substrate. The substrate includes a center region and two border regions located on opposite sides of the center region. The center region and two border regions are located in an array region. The first floating gates are located in the center region, and the second floating gates are located in one of the border regions. Each of the first floating gates has a first width, and each of the second floating gates has a second width less than the first width. There is a first spacing between the first floating gates, and there is a second spacing which is greater than the first spacing between the second floating gates.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according to the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a semiconductor liner sandwiched between the gate structure and each of the plurality of inner spacer features.

Abstract: A core test method, for testing a processing circuit with multi cores, comprising: (a) testing defects of the cores to determine at least one failed core; (b) recording the failed core; (c) performing a performance test to all of the cores to generate performance data; and (d) filtering the performance data based on the failed core recorded in the step (b).