Patents by Inventor Wei-Hao Chen
Wei-Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955404Abstract: An electronic package includes an electronic component and a heat dissipation structure, wherein the heat dissipation structure has a plurality of bonding pillars, and a metal layer is formed on the bonding pillars, so as to stably dispose the heat dissipation structure on the electronic component via the bonding pillars and the metal layer.Type: GrantFiled: December 14, 2021Date of Patent: April 9, 2024Assignee: AURAS TECHNOLOGY CO., LTD.Inventors: Jian-Dih Jeng, Chien-Yu Chen, Wei-Hao Chen
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Patent number: 11953955Abstract: A fixing mechanism is applied to an interface card assembly and an electronic apparatus. The fixing mechanism includes a movable window and an operation component. The movable window is slidably disposed on a casing of the interface card assembly. The operation component has a fixed end and a free end opposite to each other. The fixed end is disposed on the movable window. The free end is detachably engaged with the casing to position the movable window. The movable window is positioned on one of a first region and a second region of the casing for respectively fixing interface cards with different sizes to the casing.Type: GrantFiled: November 9, 2021Date of Patent: April 9, 2024Assignee: Wiwynn CorporationInventors: Wei-Li Huang, Wei-Hao Chen
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Patent number: 11956927Abstract: A case is provided, including a shell, a fan frame, and a fan module. The shell is internally provided with a backplane and a motherboard, where the motherboard is connected to the backplane along a first axis, the backplane is connected with a plug connector, the plug connector includes a plug connector body and a plurality of connection terminals, and the connection terminals are located in the plug connector body. The fan frame bears the fan module, and the fan module includes a fan assembly and a matching connector. The matching connector is connected to the fan assembly, and the matching connector is connected to the plug connector along a second axis. The matching connector includes a matching connector body and a plurality of matching terminals, and the matching terminals are located in the matching connector body. The fan frame is fixed in the shell.Type: GrantFiled: April 8, 2021Date of Patent: April 9, 2024Assignee: WISTRON CORPORATIONInventors: Jen-Hsien Lo, Wei-Hao Chen, Sheng-Chieh Tsai
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Patent number: 11944486Abstract: An analysis method and an electronic apparatus for breast image are provided. The method includes the following steps. One or more breast ultrasound images are obtained. The breast ultrasound images are used for forming a three-dimensional (3D) breast model. A volume of interest (VOI) in the breast ultrasound image is obtained by applying a detection model on the 3D breast model. The VOI is compared with a tissue segmentation result. The VOI is determined as a false positive according to a compared result between the VOI and the tissue segmentation result. The compared result includes that the VOI is located at a glandular tissue based on the tissue segmentation result. In response to the VOI being located in the glandular tissue of the tissue segmentation result, the VOI is compared with the lactiferous duct in the 3D breast model.Type: GrantFiled: July 19, 2021Date of Patent: April 2, 2024Assignee: TAIHAO MEDICAL INC.Inventors: Jen-Feng Hsu, Hong-Hao Chen, Rong-Tai Chen, Hsin-Hung Lai, Wei-Han Teng
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Patent number: 11948863Abstract: A package structure and method of forming the same are provided. The package structure includes a polymer layer, a redistribution layer, a die, and an adhesion promoter layer. The redistribution layer is disposed over the polymer layer. The die is sandwiched between the polymer layer and the redistribution layer. The adhesion promoter layer, an oxide layer, a through via, and an encapsulant are sandwiched between the polymer layer and the redistribution layer. The encapsulant is laterally encapsulates the die. The through via extends through the encapsulant. The adhesion promoter layer and the oxide layer are laterally sandwiched between the through via and the encapsulant. A bottom portion of the encapsulant is longitudinally sandwiched between the adhesion promoter layer and the polymer layer.Type: GrantFiled: February 8, 2023Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chun Cho, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Wei-Chih Chen
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Patent number: 11948904Abstract: A die includes a substrate, a conductive pad, a connector and a protection layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector includes a seed layer and a conductive post. The protection layer laterally covers the connector. Topmost surfaces of the seed layer and the conductive post and a top surface of the protection layer are level with each other.Type: GrantFiled: March 21, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
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Publication number: 20240096917Abstract: An image sensor structure includes a semiconductor substrate, a plurality of image sensing elements, a reflective element, and a high-k dielectric structure. The image sensing elements are in the semiconductor substrate. The reflective element is in the semiconductor substrate and between the image sensing elements. The high-k dielectric structure is between the reflective element and the image sensing elements.Type: ApplicationFiled: January 6, 2023Publication date: March 21, 2024Inventors: PO CHUN CHANG, PING-HAO LIN, WEI-LIN CHEN, KUN-HUI LIN, KUO-CHENG LEE
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Publication number: 20240093700Abstract: A fan cage assembly includes a cage and a handle mechanism, the handle mechanism includes a mount member including a mount portion and an extension portion respectively located at different sides of the cage and an operative member movably disposed on the extension portion of the mount member.Type: ApplicationFiled: February 17, 2023Publication date: March 21, 2024Inventor: WEI-HAO CHEN
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Patent number: 11935757Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.Type: GrantFiled: April 10, 2023Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Hao Chen, Wei-Han Lai, Ching-Yu Chang, Chin-Hsiang Lin
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Publication number: 20240088033Abstract: A method of forming a semiconductor device is provided. A transistor is formed at a first side of the substrate and a first dielectric layer is formed aside the transistor. A first metal via is formed through the first dielectric layer and aside the transistor. A first interconnect structure is formed over the first side of the substrate and electrically connected to the transistor and the first metal via. The substrate is thinned from a second side of the substrate. A capacitor is formed at the second side of the substrate and a second dielectric layer is formed aside the capacitor. A second metal via is formed through the second dielectric layer and the substrate and electrically connected to the first metal via.Type: ApplicationFiled: March 20, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Kai Chan, Chung-Hao Tsai, Chuei-Tang WANG, Wei-Ting Chen
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Publication number: 20240088078Abstract: Packaged memory devices including memory devices hybrid bonded to logic devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first memory die including a first memory cell electrically coupled to a first word line; a second memory cell electrically coupled to the first word line; and a first interconnect structure electrically coupled to the first word line; a circuitry die including a second interconnect structure, a first conductive feature of the first interconnect structure being bonded to a second conductive feature of the second interconnect structure through metal-to-metal bonds; and a word line driver electrically coupled to the first word line between the first memory cell and the second memory cell, the word line driver being electrically coupled to the first word line through the first interconnect structure and the second interconnect structure.Type: ApplicationFiled: January 4, 2023Publication date: March 14, 2024Inventors: Chung-Hao Tsai, Yih Wang, Wei-Ting Chen, Chuei-Tang Wang, Chen-Hua Yu
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Patent number: 11929434Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.Type: GrantFiled: April 15, 2022Date of Patent: March 12, 2024Assignee: eMemory Technology Inc.Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai, Wen-Hao Ching, Chun-Yuan Lo, Wei-Chen Chang
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Patent number: 11926901Abstract: A method for fabricating nonenzymatic glucose sensor, which comprises steps of: (a) providing a bottom substrate; (b) preparing a graphene layer on the bottom substrate; (c) depositing plural amount of zinc oxide (ZnO) seed crystals on the graphene layer; (d) growing the ZnO seed crystals into columnar nanorods with hydrothermal method; (e) coating a thin film of cuprous oxide (Cu2O) on the surface of the ZnO nanorods by electrochemistry-based electrodeposition; and (f) grafting single-walled carbon nanotubes (SWCNTs) on surface of the Cu2O thin film, by using Nafion fixative composited with SWCNTs. The structure of the above sensor, therefore, comprises a bottom substrate and other components orderly assembled on it, including, from inside to outside, a graphene layer, plural amount of ZnO nanorods, a Cu2O thin film, plural amount of SWCNTs, and the Nafion fixative. Accordingly, the sensor has advantages of low cost, rapid response, and easy for preservation.Type: GrantFiled: January 10, 2020Date of Patent: March 12, 2024Assignee: NATIONAL YUNLIN UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Hsi-Chao Chen, Wei-Rong Su, Yun-Cheng Yeh, Chun-Hao Chang
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Publication number: 20240080180Abstract: The federated learning system includes a moderator and client devices. Each client device performs a method for verifying model update as follows: receiving a hash function and a general model; training a client model according to the general model and raw data; calculating a difference as an update parameter between the general model and the client model, sending the update parameter to the moderator; inputting the update parameter to the hash function to generate a hash value; sending the hash value to other client devices, and receiving other hash values; summing all the hash values to generate a trust value; receiving an aggregation parameter calculated according to the update parameters; inputting the aggregation parameter to the hash function to generate a to-be-verified value; and updating the client model according to the aggregation parameter when the to-be-verified value equals the trust value.Type: ApplicationFiled: December 20, 2022Publication date: March 7, 2024Inventors: Chih-Fan HSU, Wei-Chao CHEN, Jing-Lun Huang, Ming-Ching Chang, Feng-Hao Liu
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Patent number: 11923392Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.Type: GrantFiled: January 4, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Keng-Yu Chou, Chun-Hao Chuang, Jen-Cheng Liu, Kazuaki Hashimoto, Ming-En Chen, Shyh-Fann Ting, Shuang-Ji Tsai, Wei-Chieh Chiang
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Publication number: 20240072021Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.Type: ApplicationFiled: October 26, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
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Patent number: 11913472Abstract: A centrifugal heat dissipation fan including a housing and an impeller disposed in the housing on an axis is provided. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions. A heat dissipation system of an electronic device is also provided.Type: GrantFiled: April 6, 2021Date of Patent: February 27, 2024Assignee: Acer IncorporatedInventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Chun-Chieh Wang, Shu-Hao Kuo
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Publication number: 20240064921Abstract: A server system includes a server host and a server device. The server host includes a first casing and an electrical substrate. The electrical substrate includes a first dock portion, a first metal shell, and a first magnetic piece. The first magnetic piece is in the first metal shell. The server device includes a second casing and a mainboard. The mainboard includes a second dock portion, a second metal shell, and a second magnetic piece. The second magnetic piece is in the second metal shell. The second dock portion is adapted to be docked with the first dock portion. A magnetic attraction force is generated between the first magnetic piece and the first magnetic piece, so that the second dock portion is docked with the first dock portion. Accordingly, the connection between the first dock portion and the second dock portion can be ensured.Type: ApplicationFiled: September 23, 2022Publication date: February 22, 2024Inventors: Chi-Lin Li, Wei-Hao Chen
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Patent number: 11892760Abstract: The disclosure provides a projection device, an actuator device thereof, and a projection method adapted for the actuator device. The projection method includes disposing an optical element in a frame body, and disposing a driving assembly between a base and the frame body; controlling the driving assembly to drive the frame body by a signal so that the optical element reciprocally swings relative to the base based on a first, a second, and a third moving shaft. The signal includes a first driving signal corresponding to the first moving shaft, a second driving signal corresponding to the second moving shaft, and a third driving signal corresponding to the third moving shaft. The first and the second driving signal have a first frequency; the third driving signal has a second frequency different from the first frequency. The phase difference between the first and the second driving signal is not equal to zero.Type: GrantFiled: June 21, 2022Date of Patent: February 6, 2024Assignee: Coretronic CorporationInventor: Wei-Hao Chen
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Patent number: 11856728Abstract: A liquid cooling device includes a heat dissipation shell and a dual fin module. The heat dissipation shell includes a cooling cavity, and the dual fin module is fixed in the cooling cavity to separate the cooling cavity into an upper cooling space and a lower cooling space, so that a cooling fluid enters the cooling cavity and flows into the upper cooling space and the lower cooling space to cool a chip in the lower cooling space.Type: GrantFiled: October 29, 2021Date of Patent: December 26, 2023Assignee: AURAS TECHNOLOGY CO., LTD.Inventors: Chien-Yu Chen, Wei-Hao Chen, Yuh-Shiuan Liu