Patents by Inventor Wei-Hao Liao
Wei-Hao Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11837546Abstract: The present disclosure relates to an integrated chip comprising a pair of first metal lines over a substrate. A first interlayer dielectric (ILD) layer is laterally between the pair of first metal lines. The first ILD layer comprises a first dielectric material. A pair of spacers are on opposite sides of the first ILD layer and are laterally separated from the first ILD layer by a pair of cavities. The pair of spacers comprise a second dielectric material. Further, the pair of cavities are defined by opposing sidewalls of the first ILD layer and sidewalls of the pair of spacers that face the first ILD layer.Type: GrantFiled: April 6, 2022Date of Patent: December 5, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hao Liao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai
-
Publication number: 20230387022Abstract: A semiconductor device includes a substrate, an interconnect layer disposed over the substrate and including a metal line, and a dielectric layer disposed on the interconnect layer and including a via contact. The via contact is electrically connected to the metal line and has a first dimension in a first direction greater than a second dimension in a second direction. The first direction and the second direction are perpendicular to each other, and are both perpendicular to a longitudinal direction of the via contact.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsi-Wen TIEN, Hwei-Jay CHU, Chia-Tien WU, Yung-Hsu WU, Wei-Hao LIAO, Yu-Teng DAI, Hsin-Chieh YAO, Hsin-Ping CHEN, Chih-Wei LU
-
Publication number: 20230369281Abstract: The present disclosure relates to a semiconductor structure including an interconnect structure disposed over a semiconductor substrate. A lower metal line is disposed at a first height over the semiconductor substrate and extends through a first interlayer dielectric layer. A second interlayer dielectric layer is disposed at a second height over the semiconductor substrate and comprises a first dielectric material. An upper metal line is disposed at a third height over the semiconductor substrate. A via is disposed at the second height. The via extends between the lower metal line and the upper metal line. A protective dielectric structure is disposed at the second height. The protective dielectric structure comprises a protective dielectric material and is disposed along a first set of opposing sidewalls of the via, the protective dielectric material differing from the first dielectric material.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai, Wei-Hao Liao
-
Publication number: 20230369231Abstract: The present disclosure relates to an integrated chip comprising a substrate. A first conductive wire is over the substrate. A second conductive wire is over the substrate and is adjacent to the first conductive wire. A first dielectric cap is laterally between the first conductive wire and the second conductive wire. The first dielectric cap laterally separates the first conductive wire from the second conductive wire. The first dielectric cap includes a first dielectric material. A first cavity is directly below the first dielectric cap and is laterally between the first conductive wire and the second conductive wire. The first cavity is defined by one or more surfaces of the first dielectric cap.Type: ApplicationFiled: July 27, 2023Publication date: November 16, 2023Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Yen Huang, Chia-Tien Wu
-
Publication number: 20230369099Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first dielectric layer over a substrate, a metal layer over the first dielectric layer, a first conductive structure passing through the metal layer and the first dielectric layer, a second conductive structure passing through the metal layer and the first dielectric layer, and a third conductive structure coupling the first conductive structure to the second conductive structure, and overlying a first portion of the metal layer between the first conductive structure and the second conductive structure, wherein an interface exists between the metal layer and at least one of the first conductive structure or the second conductive structure.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Inventors: Hsi-Wen TIEN, Wei-Hao LIAO, Pin-Ren DAI, Chih Wei LU, Chung-Ju LEE
-
Publication number: 20230369108Abstract: Some embodiments of the present disclosure relate to a semiconductor structure including a first conductive wire disposed over a substrate. A dielectric liner is arranged along sidewalls and an upper surface of the first conductive wire and is laterally surrounded by a first dielectric layer. The dielectric liner and the first dielectric layer are different materials. A conductive via is disposed within a second dielectric layer over the first conductive wire. The conductive via has a first lower surface disposed over the first dielectric layer and a second lower surface below the first lower surface and over the first conductive wire.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Inventors: Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Yu-Teng Dai, Hsin-Chieh Yao, Chung-Ju Lee
-
Publication number: 20230361029Abstract: An interconnect structure includes a dielectric layer, a first conductive feature, a second conductive feature, a third conductive feature, and a dielectric fill. The first conductive feature is disposed in the dielectric layer. The second conductive feature is disposed over the first conductive feature. The second conductive feature includes a first conductive layer disposed over the first conductive feature, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer. The first conductive layer, the second conductive layer and the third conductive layer have substantially the same width. The third conductive feature is disposed over the dielectric layer. The dielectric fill is disposed over the dielectric layer between the second conductive feature and the third conductive feature.Type: ApplicationFiled: July 20, 2023Publication date: November 9, 2023Inventors: Wei-Hao Liao, Hsi-Wen Tien, Yu-Teng Dai, Chih Wei Lu, Hsin-Chieh Yao, Chung-Ju Lee
-
Patent number: 11798840Abstract: Some embodiments of the present disclosure relate to a semiconductor structure including a first conductive wire disposed over a substrate. A dielectric liner is arranged along sidewalls and an upper surface of the first conductive wire and is laterally surrounded by a first dielectric layer. The dielectric liner and the first dielectric layer are different materials. A conductive via is disposed within a second dielectric layer over the first conductive wire. The conductive via has a first lower surface disposed over the first dielectric layer and a second lower surface below the first lower surface and over the first conductive wire.Type: GrantFiled: June 3, 2021Date of Patent: October 24, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Yu-Teng Dai, Hsin-Chieh Yao, Chung-Ju Lee
-
Patent number: 11798910Abstract: The present disclosure relates to a semiconductor structure including an interconnect structure disposed over a semiconductor substrate. A lower metal line is disposed at a first height over the semiconductor substrate and extends through a first interlayer dielectric layer. A second interlayer dielectric layer is disposed at a second height over the semiconductor substrate and comprises a first dielectric material. An upper metal line is disposed at a third height over the semiconductor substrate. A via is disposed at the second height. The via extends between the lower metal line and the upper metal line. A protective dielectric structure is disposed at the second height. The protective dielectric structure comprises a protective dielectric material and is disposed along a first set of opposing sidewalls of the via, the protective dielectric material differing from the first dielectric material.Type: GrantFiled: July 20, 2022Date of Patent: October 24, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai, Wei-Hao Liao
-
Publication number: 20230335608Abstract: A semiconductor structure includes a substrate, a gate structure, source/drain epitaxial structures, a contact structure, a first via structure, a metal line, a hard mask layer, a spacer layer, and a second via structure. The gate structure is formed over the substrate. The source/drain epitaxial structures are formed on opposite sides of the gate structure. The contact structure is formed over one of the source/drain epitaxial structures. The first via structure is formed over the contact structure. The metal line is electrically connected to the first via structure. The hard mask layer is formed over the metal line. The spacer layer is formed over a top surface of the hard mask layer and over a sidewall of metal line. The second via structure is formed over the metal line through the spacer layer.Type: ApplicationFiled: June 26, 2023Publication date: October 19, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hao LIAO, Hsi-Wen TIEN, Chih-Wei LU, Yu-Teng DAI, Hsin-Chieh YAO, Chung-Ju LEE
-
Publication number: 20230337545Abstract: An MRAM device includes a bottom electrode over a substrate, a magnetic tunnel junction (MTJ) structure on the bottom electrode and a top electrode on the MTJ structure. The MRAM device also includes spacers on sidewalls of the top electrode and the MTJ structure. The MRAM device further includes a first etch stop layer on the spacers. A bottommost surface of the first etch stop layer covers a topmost surface of the spacers. In addition, the MRAM device includes a top electrode via on the top electrode and the first etch stop layer.Type: ApplicationFiled: June 16, 2023Publication date: October 19, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hao LIAO, Hsi-Wen TIEN, Chih-Wei LU, Pin-Ren DAI, Chung-Ju LEE
-
Patent number: 11776845Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first dielectric layer over a substrate, a metal layer over the first dielectric layer, a first conductive structure passing through the metal layer and the first dielectric layer, a second conductive structure passing through the metal layer and the first dielectric layer, and a third conductive structure coupling the first conductive structure to the second conductive structure, and overlying a first portion of the metal layer between the first conductive structure and the second conductive structure, wherein an interface exists between the metal layer and at least one of the first conductive structure or the second conductive structure.Type: GrantFiled: November 29, 2021Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu, Chung-Ju Lee
-
Patent number: 11756884Abstract: An interconnect structure includes dielectric layer, a first conductive feature, a second conductive feature, a third conductive feature, and a dielectric fill. The first conductive feature is disposed in the dielectric layer. The second conductive feature is disposed over the first conductive feature. The second conductive feature includes a first conductive layer disposed over the first conductive feature, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer. The first conductive layer, the second conductive layer and the third conductive layer have substantially the same width. The third conductive feature is disposed over the dielectric layer. The dielectric fill is disposed over the dielectric layer between the second conductive feature and the third conductive feature.Type: GrantFiled: May 6, 2021Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Hao Liao, Hsi-Wen Tien, Yu-Teng Dai, Chih Wei Lu, Hsin-Chieh Yao, Chung-Ju Lee
-
Publication number: 20230275028Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.Type: ApplicationFiled: May 3, 2023Publication date: August 31, 2023Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai, Wei-Hao Liao
-
Patent number: 11723282Abstract: An MRAM device includes a bottom electrode over a substrate, a magnetic tunnel junction (MTJ) structure on the bottom electrode, and a top electrode on the MTJ structure. The MRAM device also includes spacers on sidewalls of the top electrode and the MTJ structure, and a first dielectric layer surrounding the spacers. The MRAM device further includes a patterned etch stop layer on the first dielectric layer and the spacers. In addition, the MRAM device includes a second dielectric layer on the patterned etch stop layer, and a top electrode via embedded in the second dielectric layer and in contact with the top electrode and the patterned etch stop layer.Type: GrantFiled: April 15, 2021Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacuturing Company, Ltd.Inventors: Wei-Hao Liao, Hsi-Wen Tien, Chih-Wei Lu, Pin-Ren Dai, Chung-Ju Lee
-
Publication number: 20230230881Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a conductive line over the substrate. The semiconductor device structure also includes a catalyst structure over the conductive line and a carbon-containing conductive via directly on the catalyst structure. The semiconductor device structure further includes a dielectric layer surrounding the carbon-containing conductive via.Type: ApplicationFiled: January 18, 2022Publication date: July 20, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hao LIAO, Hsi-Wen TIEN, Yu-Teng DAI, Chih-Wei LU, Hsin-Chieh YAO, Hwei-Jay CHU
-
Patent number: 11688782Abstract: A semiconductor structure includes a gate structure over a substrate. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The structure also includes a contact structure formed over the source/drain epitaxial structure. The structure also includes a first via structure formed over the contact structure. The structure also includes a metal line electrically connected to the first via structure. The structure also includes a spacer layer formed over the sidewall and over a portion of a top surface of the metal line. The structure also includes a second via structure formed over the metal line through the spacer layer.Type: GrantFiled: March 25, 2021Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Wei-Hao Liao, Hsi-Wen Tien, Chih-Wei Lu, Yu-Teng Dai, Hsin-Chieh Yao, Chung-Ju Lee
-
Publication number: 20230178381Abstract: An semiconductor device includes a first dielectric layer, an etch stop layer, an interconnect structure, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The interconnect structure includes a conductive via in the first dielectric layer and the etch stop layer, a conductive line over the conductive via, an intermediate conductive layer over the conductive line, and a conductive pillar over the intermediate conductive layer. The interconnect structure is electrically conductive at least from a top of the conductive pillar to a bottom of the conductive via. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, wherein a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.Type: ApplicationFiled: January 30, 2023Publication date: June 8, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsi-Wen TIEN, Wei-Hao LIAO, Chih-Wei LU, Pin-Ren DAI, Chung-Ju LEE
-
Publication number: 20230170254Abstract: In one embodiment, a method of forming metal interconnects uses a direct metal etch approach to form and fill the metal gap. The method may include directly etching a metal layer to form metal patterns. The metal patterns may be spaced apart from one another by recesses. A dielectric spacer may be formed extending along the sidewalls of each of the recesses. The recesses may be filled with a conductive material to form a second set of metal patterns. By directly etching the metal film, the technique allows for reduced line width roughness. The disclosed structure may have the advantages of increased reliability, better RC performance and reduced parasitic capacitance.Type: ApplicationFiled: January 27, 2023Publication date: June 1, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih-Wei Lu, Chung-Ju Lee
-
Patent number: 11652054Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.Type: GrantFiled: April 21, 2021Date of Patent: May 16, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai, Wei-Hao Liao