Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.

Abstract: The disclosure provides a method of active immunotherapy for a cancer patient, comprising administering vaccines against Globo series antigens (i.e., Globo H, SSEA-3 and SSEA-4). Specifically, the method comprises administering Globo H-CRM197 (OBI-833/821) in patients with cancer. The disclosure also provides a method of selecting a cancer patient who is suitable as treatment candidate for immunotherapy. Exemplary immune response can be characterized by reduction of the severity of disease, including but not limited to, prevention of disease, delay in onset of disease, decreased severity of symptoms, decreased morbidity and delayed mortality.

Abstract: An electronic device includes a substrate, a driving element, a first insulating layer, a pixel electrode layer, and a common electrode layer. The driving element is disposed on the substrate. The first insulating layer is disposed on the driving element. The pixel electrode layer is disposed on the first insulating layer. The first insulating layer comprises a hole, and the pixel electrode layer is electrically connected to the driving element through the hole. The common electrode layer is disposed on the pixel electrode layer. The common electrode layer comprises a slit, and the slit has an edge, and the edge is disposed in the hole.

Abstract: Embodiments of the present disclosure relates to a method for forming a semiconductor device structure. The method includes including forming one or more conductive features in a first interlayer dielectric (ILD), forming an etch stop layer on the first ILD, forming a second ILD over the etch stop layer, forming one or more openings through the second ILD and the etch stop layer to expose a top surface of the one or more first conductive features, wherein the one or more openings are formed by a first etch process in a first process chamber, exposing the one or more openings to a second etch process in a second process chamber so that the shape of the or more openings is elongated, and filling the one or more openings with a conductive material.

Abstract: A case is provided, including a shell, a fan frame, and a fan module. The shell is internally provided with a backplane and a motherboard, where the motherboard is connected to the backplane along a first axis, the backplane is connected with a plug connector, the plug connector includes a plug connector body and a plurality of connection terminals, and the connection terminals are located in the plug connector body. The fan frame bears the fan module, and the fan module includes a fan assembly and a matching connector. The matching connector is connected to the fan assembly, and the matching connector is connected to the plug connector along a second axis. The matching connector includes a matching connector body and a plurality of matching terminals, and the matching terminals are located in the matching connector body. The fan frame is fixed in the shell.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. The semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. The conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. A top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.

Abstract: A method of forming a semiconductor device is provided. A transistor is formed at a first side of the substrate and a first dielectric layer is formed aside the transistor. A first metal via is formed through the first dielectric layer and aside the transistor. A first interconnect structure is formed over the first side of the substrate and electrically connected to the transistor and the first metal via. The substrate is thinned from a second side of the substrate. A capacitor is formed at the second side of the substrate and a second dielectric layer is formed aside the capacitor. A second metal via is formed through the second dielectric layer and the substrate and electrically connected to the first metal via.

Abstract: Packaged memory devices including memory devices hybrid bonded to logic devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first memory die including a first memory cell electrically coupled to a first word line; a second memory cell electrically coupled to the first word line; and a first interconnect structure electrically coupled to the first word line; a circuitry die including a second interconnect structure, a first conductive feature of the first interconnect structure being bonded to a second conductive feature of the second interconnect structure through metal-to-metal bonds; and a word line driver electrically coupled to the first word line between the first memory cell and the second memory cell, the word line driver being electrically coupled to the first word line through the first interconnect structure and the second interconnect structure.

Abstract: A semiconductor device includes a die, an encapsulant over a front-side surface of the die, a redistribution structure on the encapsulant, a thermal module coupled to the back-side surface of the die, and a bolt extending through the redistribution structure and the thermal module. The die includes a chamfered corner. The bolt is adjacent to the chamfered corner.

Abstract: Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Dies of the pair of dies are disposed side by side. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.

Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: A bootstrap circuit including a receiving circuit, a switched capacitor module and a booting circuit is provided. The receiving circuit receives an input signal to selectively output an output signal according to a control signal. The switched capacitor module is coupled to the input signal, and is arranged for generating the control signal according to the input signal. The booting circuit is coupled to the receiving circuit, and is arranged for applying an initial voltage when the control signal starts to enable the transistor, to increase a voltage level of the control signal.

Abstract: A bootstrap circuit including a receiving circuit, a switched capacitor module and a booting circuit is provided. The receiving circuit receives an input signal to selectively output an output signal according to a control signal. The switched capacitor module is coupled to the input signal, and is arranged for generating the control signal according to the input signal. The booting circuit is coupled to the receiving circuit, and is arranged for applying an initial voltage when the control signal starts to enable the transistor, to increase a voltage level of the control signal.

Abstract: A metal-oxide-metal (MOM) capacitor is provided in the present invention. The MOM capacitor includes a capacitor element, wherein the capacitor element includes a first electrode and a second electrode. A projection of the first electrode includes a closed pattern in the vertical projection direction. A projection of the second electrode is surrounded by the closed pattern of the projection of the first electrode in the vertical projection direction.

Abstract: A metal-oxide-metal (MOM) capacitor is provided in the present invention. The MOM capacitor includes a capacitor element, wherein the capacitor element includes a first electrode and a second electrode. A projection of the first electrode includes a closed pattern in the vertical projection direction. A projection of the second electrode is surrounded by the closed pattern of the projection of the first electrode in the vertical projection direction.