Patents by Inventor Wei-Hao Wu

Wei-Hao Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10840133
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate; a first conductive feature and a second conductive feature disposed on the semiconductor substrate; and a staggered dielectric feature interposed between the first and second conductive feature. The staggered dielectric feature includes first dielectric layers and second dielectric layers being interdigitated. The first dielectric layers include a first dielectric material and the second dielectric layers include a second dielectric material being different from the first dielectric material.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang Lin, Teng-Chun Tsai, Wei-Hao Wu
  • Publication number: 20200350113
    Abstract: A coil module is provided, including a second coil mechanism. The second coil mechanism includes a third coil assembly and a second base corresponding to the third coil assembly. The second base has a positioning assembly corresponding to a first coil mechanism.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 5, 2020
    Inventors: Feng-Lung CHIEN, Tsang-Feng WU, Yuan HAN, Tzu-Chieh KAO, Chien-Hung LIN, Kuang-Lun LEE, Hsiang-Hui HSU, Shu-Yi TSUI, Kuo-Jui LEE, Kun-Ying LEE, Mao-Chun CHEN, Tai-Hsien YU, Wei-Yu CHEN, Yi-Ju LI, Kuei-Yuan CHANG, Wei-Chun LI, Ni-Ni LAI, Sheng-Hao LUO, Heng-Sheng PENG, Yueh-Hui KUAN, Hsiu-Chen LIN, Yan-Bing ZHOU, Chris T. Burket
  • Publication number: 20200303194
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a substrate, a fin structure formed over the substrate, and an isolation structure formed over the substrate. The fin structure protrudes from the isolation structure. The FinFET device structure further includes a fin isolation structure formed over the isolation structure and a metal gate structure formed over the fin structure and the fin isolation structure.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jia-Ni YU, Zhi-Chang LIN, Wei-Hao WU, Huan-Chieh SU, Chung-Wei HSU, Chih-Hao WANG
  • Publication number: 20200295772
    Abstract: A signal processing system includes an analog-to-digital converter (ADC) that is used to convert a first analog value into a first digital value and convert a second analog value into a second digital value. The ADC includes a first digital-to-analog converter (DAC) circuit and a second DAC circuit operating in different voltage domains. A first bit segment and a second bit segment of each digital value are determined via the first DAC circuit and the second DAC circuit, respectively. An analog injection value is injected to the second analog value, the analog injection value is converted from a digital injection value formed by a subset of bits of the second bit segment of the first digital value, and the second bit segment of the second digital value is derived from injecting the digital injection value to a digital value determined by the second DAC circuit.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 17, 2020
    Inventors: Wei-Hsiang Huang, Yun-Shiang Shu, Su-Hao Wu
  • Publication number: 20200281084
    Abstract: Examples of hinge assemblies are described. In an example implementation, a hinge assembly includes hinge elements which are interconnected to move the hinge assembly between a folded position and an unfolded position. The hinge assembly further includes elastic members disposed between the hinge elements at a first side and a second side thereof. When the hinge assembly is moved from the unfolded position towards the folded position, elastic members at the first side are decompressed and elastic members at the second side are stretched. When the hinge assembly is moved from the folded position towards the unfolded position, elastic members at the first side are compressed and the elastic members at the second side are destretched.
    Type: Application
    Filed: October 6, 2017
    Publication date: September 3, 2020
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Wei-Chung Chen, Kuan-Ting Wu, Chi-Hao Chang
  • Patent number: 10755977
    Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device includes a substrate, a gate stack, a gate spacer, a conductive feature, and a conductive cap. The substrate has a source/drain region. The gate stack is on the substrate. The gate spacer is alongside the gate stack. The conductive feature is on the source/drain region. The conductive cap is on the conductive feature and has a top in a position lower than a top of the gate spacer.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Chuan You, Chia-Hao Chang, Wei-Hao Wu, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 10750144
    Abstract: A smart lighting device includes an illumination module, an image projection module and a projection mode switching module. The image projection module is pivoted to the illumination module and has a plurality of operation modes. The image projection module rotates relative to the illumination module and is switched among a standby mode and the operation modes. The projection mode switching module is configured to sense a rotation angle of the image projection module with respect to the illumination module. A brightness value of the illumination module and an image frame of the image projection module are adjusted according to the rotation angle.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: August 18, 2020
    Assignee: Compal Electronics, Inc.
    Inventors: Wei-Jun Wang, Wen-Yi Chiu, Ting-Wei Wu, Chia-Min Liao, Tse-Hsun Pang, Kun-Hsuan Chang, Yu-Hao Tseng, Jui-Tsen Huang
  • Publication number: 20200251566
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device including a gate structure. The semiconductor device further includes a pair of spacer segments on a semiconductor substrate. A high-? gate dielectric structure overlies the semiconductor substrate. The high-? gate dielectric structure is laterally between and borders the spacer segments. The gate structure overlies the high-k gate dielectric structure and has a top surface about even with a top surface of the spacer segments. The gate structure includes a metal structure and a gate body layer. The gate body layer has a top surface that is vertically offset from a top surface of the metal structure and further has a lower portion cupped by the metal structure.
    Type: Application
    Filed: September 24, 2019
    Publication date: August 6, 2020
    Inventors: Wei Cheng Wu, Alexander Kalnitsky, Shih-Hao Lo, Hung-Pin Ko
  • Publication number: 20200251456
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
    Type: Application
    Filed: April 23, 2020
    Publication date: August 6, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
  • Publication number: 20200235159
    Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first image sensor disposed within a first substrate and a second image sensor disposed within a second substrate. The second substrate has a first side facing the first substrate. The first side includes angled surfaces defining one or more recesses within the first side. A band-pass filter is arranged between the first substrate and the second substrate and is configured to reflect electromagnetic radiation that is within a first range of wavelengths.
    Type: Application
    Filed: April 1, 2020
    Publication date: July 23, 2020
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Hau Wu
  • Patent number: 10717714
    Abstract: A reactive UV absorber suitable for polyurethane is provided. The reactive UV absorber is a compound of formula 1: wherein R1 is H or Cl.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: July 21, 2020
    Assignee: CHITEC TECHNOLOGY CO., LTD.
    Inventors: Chingfan Chris Chiu, Huang-min Wu, Wei-chun Chang, Chi-feng Wu, Ching-hao Cheng, Shao-hsuan Wu
  • Publication number: 20200227460
    Abstract: Various embodiments of the present application are directed to a narrow band filter with high transmission and an image sensor comprising the narrow band filter. In some embodiments, the filter comprises a first distributed Bragg reflector (DBR), a second DBR, a defect layer between the first and second DBRs, and a plurality of columnar structures. The columnar structures extend through the defect layer and have a refractive index different than a refractive index of the defect layer. The first and second DBRs define a low transmission band, and the defect layer defines a high transmission band dividing the low transmission band. The columnar structures shift the high transmission band towards lower or higher wavelengths depending upon a refractive index of the columnar structures and a fill factor of the columnar structures.
    Type: Application
    Filed: April 1, 2020
    Publication date: July 16, 2020
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Hau Wu
  • Publication number: 20200227461
    Abstract: Various embodiments of the present application are directed to a narrow band filter with high transmission and an image sensor comprising the narrow band filter. In some embodiments, the filter comprises a first distributed Bragg reflector (DBR), a second DBR, a defect layer between the first and second DBRs, and a plurality of columnar structures. The columnar structures extend through the defect layer and have a refractive index different than a refractive index of the defect layer. The first and second DBRs define a low transmission band, and the defect layer defines a high transmission band dividing the low transmission band. The columnar structures shift the high transmission band towards lower or higher wavelengths depending upon a refractive index of the columnar structures and a fill factor of the columnar structures.
    Type: Application
    Filed: April 1, 2020
    Publication date: July 16, 2020
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Hau Wu
  • Publication number: 20200199084
    Abstract: A reactive UV absorber suitable for polyurethane is provided. The reactive UV absorber is a compound of formula 1: wherein R1 is H or Cl.
    Type: Application
    Filed: July 7, 2017
    Publication date: June 25, 2020
    Inventors: Chingfan Chris CHIU, Huang-min WU, Wei-chun CHANG, Chi-feng WU, Ching-hao CHENG, Shao-hsuan WU
  • Patent number: 10679856
    Abstract: A method for forming a FinFET device structure is provided. The method for forming a FinFET device structure includes forming a fin structure and a fin isolation structure over a substrate, and forming a metal stack over the fin structure and the fin isolation structure. The method for forming a FinFET device structure also includes partially removing the metal stack so that a top surface of the fin isolation structure is exposed, and forming a dielectric material over the metal stack and covering the top surface of the fin isolation structure. The method for forming a FinFET device structure further includes patterning the dielectric material and the metal stack to form a metal gate structure and an insulating structure over the metal gate structure.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Ni Yu, Zhi-Chang Lin, Wei-Hao Wu, Huan-Chieh Su, Chung-Wei Hsu, Chih-Hao Wang
  • Publication number: 20200152379
    Abstract: An inductor and a method for manufacturing same are provided. The method includes: bending two ends of a wound coil towards the same side; bending the two bent ends to respectively form contact sections at the tail ends, the two contact sections are located in the same plane; and encapsulating the coil in an encapsulation body, the two contact sections are exposed outside the encapsulation body.
    Type: Application
    Filed: October 29, 2019
    Publication date: May 14, 2020
    Inventors: Hsi-Ho Hsu, Ming-Ting Tsai, Wei-Gen Chung, Chen-Hao Yu, Tsung-Han Wu, Hsiang-Jui Hung
  • Patent number: 10651225
    Abstract: In some embodiments, the present disclosure relates to a three-dimensional integrated chip. The three-dimensional integrated chip includes a first integrated chip (IC) die and a second IC die. The first IC die has a first image sensor element configured to generate electrical signals from electromagnetic radiation within a first range of wavelengths. The second IC die has a second image sensor element configured to generate electrical signals from electromagnetic radiation within a second range of wavelengths that is different than the first range of wavelengths. A first band-pass filter is arranged between the first IC die and the second IC die and is configured to reflect electromagnetic radiation that is within the first range of wavelengths.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Hau Wu
  • Patent number: 10650786
    Abstract: An automatically brightness adjusting electronic device and a brightness adjusting method are provided. The method comprises: sensing an environmental light intensity; generating a brightness adjustment signal according to the environmental light intensity via a second control unit; and adjusting a display brightness of a display unit according to the brightness adjustment signal via a first control unit or the second control unit.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: May 12, 2020
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chin-Hung Lin, Wei-Chung Hung, Huai-Hao Syu, Tzu-Ping Lin, Chia-Po Chou, Tsung-Lin Wu, Han-Wei Tang, Yi-Ching Chen, Chih-Lung Lin, Ping-Fu Hsieh
  • Patent number: 10651220
    Abstract: Various embodiments of the present application are directed to a narrow band filter with high transmission and an image sensor comprising the narrow band filter. In some embodiments, the filter comprises a first distributed Bragg reflector (DBR), a second DBR, a defect layer between the first and second DBRs, and a plurality of columnar structures. The columnar structures extend through the defect layer and have a refractive index different than a refractive index of the defect layer. The first and second DBRs define a low transmission band, and the defect layer defines a high transmission band dividing the low transmission band. The columnar structures shift the high transmission band towards lower or higher wavelengths depending upon a refractive index of the columnar structures and a fill factor of the columnar structures.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Hau Wu
  • Patent number: 10636775
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu