Abstract: Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device precursor. The semiconductor device precursor includes a substrate, source/drain regions on the substrate, dummy gate stacks separating the source/drain regions on the substrate and a doped region under the dummy gate stacks. The dummy gate stack is removed to form a gate trench. The doped region in the gate trench is recessed to form a channel trench. A channel layer is deposited in the channel trench to form a channel region and then a high-k (HK) dielectric layer and a metal gate (MG) are deposited on the channel region.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device precursor. The semiconductor device precursor includes a substrate, source/drain regions on the substrate, dummy gate stacks separating the source/drain regions on the substrate and a doped region under the dummy gate stacks. The dummy gate stack is removed to form a gate trench. The doped region in the gate trench is recessed to form a channel trench. A channel layer is deposited in the channel trench to form a channel region and then a high-k (HK) dielectric layer and a metal gate (MG) are deposited on the channel region.

Abstract: A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate, first fins on the substrate, isolation regions on sides of the first fins, source/drain features on the substrate and dummy gate stacks separating the source/drain features on the substrate. The dummy gate stack is removed to expose the first fins and then the first fins are recessed to form channel trenches. A channel layer is deposited in the channel trenches and then is recessed. Then the isolation regions are recessed to laterally expose at least a portion of the recessed channel layer to form second fins. A high-k (HK) dielectric layer and a metal gate (MG) layer are deposited on the second fins.

Abstract: A method of fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET) device on a substrate includes doping a channel region of the MOSFET device with dopants of a first type. A source and a drain are formed in the substrate with dopants of a second type. Selective dopant deactivation is performed in a region underneath a gate of the MOSFET device.

Abstract: Methods and structures for forming semiconductor FinFET devices with superior repeatability and reliability include providing APT (anti-punch through) layer accurately formed beneath a semiconductor fins, are provided. Both the n-type and p-type APT layers are formed prior to the formation of the material from which the semiconductor fin is formed. In some embodiments, barrier layers are added between the accurately positioned APT layer and the semiconductor fin. Ion implantation methods and epitaxial growth methods are used to form appropriately doped APT layers in a semiconductor substrate surface. The fin material is formed over the APT layers using epitaxial growth/deposition methods.

Abstract: Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.

Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.

Abstract: This invention discloses a system and method for suppressing negative bias temperature instability in PMOS transistors, the system comprises a PMOS transistor having a source connected to a power supply, and a voltage control circuitry configured to output a first and a second voltage level, the first and second voltage levels being different from each other, the first voltage level is lower than the power supply voltage, the second voltage level is equal to or higher than the power supply voltage, wherein when the PMOS transistor is turned on, the first voltage level is applied to a substrate of the PMOS transistor, and when the PMOS transistor is turned off, the second voltage level is applied to the substrate of the PMOS transistor.