Abstract: Efficient data path architecture for flash devices requiring multi-pass programming utilizes an external memory as an intermediate buffer to store the encoded data used for a first pass programming of the flash device. The stored encoded data can be read from the external memory for subsequent passes programming instead of fetching the data from an on-chip memory, which stores the data received from a host system. Thus, the on-chip memory can be made available to speed up the next data transfer from the host system.

Abstract: A first memory location stores circulant contents of portions A, C, E, and B of a parity check matrix H. A second memory location stores circulant column counts of the portions A, C, E, and B. A third memory location stores a dense matrix equal to (ET?1B+D)?1, where T is an identity matrix and D and T are also portions of the parity check matrix H. First and second parity information is generated in response to receiving information data. Generating the first and second parity information includes accessing the circular content of the portions A, C, E, and B of a parity check matrix H and accessing the circulant column counts of the portions A, C, E, and B.

Abstract: Memory systems may include a memory portion, and a controller suitable for receiving information data, generating first stage data, generating a first portion parity information, generating a second portion parity information based at least in part on the first portion parity information and the first stage data, and outputting the second portion parity information.

Abstract: A first write data and a second write data destined for a first solid state storage channel and a second solid state storage channel, respectively, is received. The first write data is chopped using a chopping factor in order to obtain (1) a first piece of chopped write data destined for the first solid state storage channel and (2) a second piece of chopped write data destined for the first solid state storage channel. The second write data is chopped using the chopping factor in order to obtain (1) a third piece of chopped write data destined for the second solid state storage channel and (2) a fourth piece of chopped write data destined for the second solid state storage channel.

Abstract: Techniques are described for optimizing a parity-check matrix for a low density parity check (LDPC) encoder. In an example, a first parity-check matrix is accessed. Based on a set of rules, an independent set of check nodes and variable nodes is determined. The set of rules specifies that a check node associated with the first parity-check matrix belongs to the independent set when the check node is connected to only one variable node from the independent set. The set of rules further specifies that a variable node associated with the first parity-check matrix belongs to the independent set when the variable node is connected to only one check node from the independent set. A size of the independent set is based on the set of rules. A second parity-check matrix is generated by at least applying a permutation to the first parity-check matrix based on the independent set.

Abstract: Efficient data path architecture for flash devices requiring multi-pass programming utilizes an external memory as an intermediate buffer to store the encoded data used for a first pass programming of the flash device. The stored encoded data can be read from the external memory for subsequent passes programming instead of fetching the data from an on-chip memory, which stores the data received from a host system. Thus, the on-chip memory can be made available to speed up the next data transfer from the host system.

Abstract: Techniques are described for optimizing a parity-check matrix for a low density parity check (LDPC) encoder. In an example, a first parity-check matrix is accessed. Based on a set of rules, an independent set of check nodes and variable nodes is determined. The set of rules specifies that a check node associated with the first parity-check matrix belongs to the independent set when the check node is connected to only one variable node from the independent set. The set of rules further specifies that a variable node associated with the first parity-check matrix belongs to the independent set when the variable node is connected to only one check node from the independent set. A size of the independent set is based on the set of rules. A second parity-check matrix is generated by at least applying a permutation to the first parity-check matrix based on the independent set.

Abstract: A first memory location stores circulant contents of portions A, C, E, and B of a parity check matrix H. A second memory location stores circulant column counts of the portions A, C, E, and B. A third memory location stores a dense matrix equal to (ET?1B+D)?1, where T is an identity matrix and D and T are also portions of the parity check matrix H. First and second parity information is generated in response to receiving information data. Generating the first and second parity information includes accessing the circular content of the portions A, C, E, and B of a parity check matrix H and accessing the circulant column counts of the portions A, C, E, and B.

Abstract: Memory systems may include a memory portion, and a controller suitable for receiving information data, generating first stage data, generating a first portion parity information, generating a second portion parity information based at least in part on the first portion parity information and the first stage data, and outputting the second portion parity information.

Abstract: A data compression system and a data compression method using the same are provided. The data compression method includes acquiring original data from a memory and performs image processing and quantization on the original data to transform the original data into a quantization matrix. The data compression method then transforms the quantization matrix into a digital sequence based on a coding table and compares the data volume of the digital sequence and a target volume to generate a volume difference. The data compression method transforms the digital sequence into an inverse quantization matrix based on the volume difference and then transforms the inverse quantization matrix into a modified digital sequence based on the volume difference. The data compression method repeats the processes until the data volume of the digital sequence is substantially equal to a target volume or within an acceptable range of the target volume.

Abstract: A device and method is provided to selectively modify the transmission performance of a frame data. Through a parallel transmission interface, the frame data is transmitted under a corresponding interface protocol and transmitted toward an image display. The method first detects a data size of the frame data and then provides a transmission control signal based on the detection of the data size. Next, selectively divide the frame data by a factor M based on the transmission control signal. Furthermore, transmit the divided frame data at a raised clock rate based on the factor M. Afterwards, temporarily store the divided frame data about to be transmitted toward the image display until the whole frame data is transmitted.

Abstract: A data compression system and a data compression method using the same are provided. The data compression method includes acquiring original data from a memory and performs image processing and quantization on the original data to transform the original data into a quantization matrix. The data compression method then transforms the quantization matrix into a digital sequence based on a coding table and compares the data volume of the digital sequence and a target volume to generate a volume difference. The data compression method transforms the digital sequence into an inverse quantization matrix based on the volume difference and then transforms the inverse quantization matrix into a modified digital sequence based on the volume difference. The data compression method repeats the processes until the data volume of the digital sequence is substantially equal to a target volume or within an acceptable range of the target volume.

Abstract: The present invention discloses a multi-channel multi-media data processing method, comprising the steps of: providing a demodulator circuit and a multi-media processing circuit, the multi-media processing circuit including a DRAM; receiving multi-channel analog signals, and performing analog-to-digital conversion and demodulation on the signals by the demodulator circuit; storing the converted and demodulated multi-channel signals in the DRAM; and reading the signals of at least one channel from the DRAM.

Abstract: A device and method is provided to selectively modify the transmission performance of a frame data. Through a parallel transmission interface, the frame data is transmitted under a corresponding interface protocol and transmitted toward an image display. The method first detects a data size of the frame data and then provides a transmission control signal based on the detection of the data size. Next, selectively divide the frame data by a factor M based on the transmission control signal. Furthermore, transmit the divided frame data at a raised clock rate based on the factor M. Afterwards, temporarily store the divided frame data about to be transmitted toward the image display until the whole frame data is transmitted.

Abstract: The present invention discloses a multi-media data processing method for use in an integrated circuit having an error correction circuit, the method comprising the steps of: receiving broadcasted analog data; converting the analog data to digital data; and storing the digital data into a main memory without error correction, wherein the digital data stored in the main memory are subject to error correction only when it is required, but are not subject to error correction if it is not required.

Abstract: The present invention discloses a multi-channel multi-media data processing method, comprising the steps of: providing a demodulator circuit and a multi-media processing circuit, the multi-media processing circuit including a DRAM; receiving multi-channel analog signals, and performing analog-to-digital conversion and demodulation on the signals by the demodulator circuit; storing the converted and demodulated multi-channel signals in the DRAM; and reading the signals of at least one channel from the DRAM.