Patents by Inventor Wei-Heng Hsu
Wei-Heng Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11769526Abstract: Magnetic recording media with a thermal spin injection layer that induces a spin injection in a magnetic recording layer in response to a thermal gradient in the thermal spin injection layer. The thermal spin injection layer may comprise an antiferromagnetic, a ferromagnetic, or a ferrimagnetic material that demonstrates a Spin Seebeck effect. In turn, when heating the magnetic recording media (e.g., with a near field transducer of a HAMR drive), the thermal gradient may be established in the thermal spin injection layer. A resulting spin torque field may assist in switching a magnetic domain in the magnetic recording layer by providing an assistive field to at least initiate switching of the magnetic domain. In turn, more reliable or efficient operation of a storage drive comprising the magnetic recording media may be realized.Type: GrantFiled: August 16, 2022Date of Patent: September 26, 2023Assignee: SEAGATE TECHNOLOGY LLCInventors: Yichun Fan, Javier Ignacio Guzman, Ali Ghoreyshi, Wei-Heng Hsu, Pin-Wei Huang
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Patent number: 10312235Abstract: A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.Type: GrantFiled: February 8, 2018Date of Patent: June 4, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wen-Yin Weng, Cheng-Tung Huang, Wei-Heng Hsu, Yu-Ming Lin, Ya-Ru Yang
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Publication number: 20180166444Abstract: A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.Type: ApplicationFiled: February 8, 2018Publication date: June 14, 2018Inventors: Wen-Yin Weng, Cheng-Tung Huang, Wei-Heng Hsu, Yu-Ming Lin, Ya-Ru Yang
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Patent number: 9929154Abstract: A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.Type: GrantFiled: November 13, 2014Date of Patent: March 27, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wen-Yin Weng, Cheng-Tung Huang, Wei-Heng Hsu, Yu-Ming Lin, Ya-Ru Yang
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Publication number: 20160141288Abstract: A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.Type: ApplicationFiled: November 13, 2014Publication date: May 19, 2016Inventors: Wen-Yin Weng, Cheng-Tung Huang, Wei-Heng Hsu, Yu-Ming Lin, Ya-Ru Yang
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Patent number: 9299839Abstract: A P-type field effect transistor includes: a gate area; an insulated area, adjacent to the gate area; a source region and a drain region made by silicon germanium, respectively, adjacent to the second side of the insulated area; a channel area, adjacent to the insulated area and formed between the source region and the drain region; a conductive layer, electrically connected to the source region and the drain region, respectively; and a plurality of capping layers, connected between the conductive layer and the source/drain regions, wherein the silicon layer(s) and the silicon germanium layer(s) are stacked alternately, and of which a silicon layer contacts the source/drain silicon germanium regions, while a silicon germanium layer contacts the conductive layer. The present invention also provides a complementary metal oxide semiconductor transistor including the P-type field effect transistor mentioned above.Type: GrantFiled: October 3, 2014Date of Patent: March 29, 2016Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Wen-Yin Weng, Cheng-Tung Huang, Wei-Heng Hsu, Yi-Ting Wu, Yu-Ming Lin, Jen-Yu Wang
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Publication number: 20160064563Abstract: A P-type field effect transistor includes: a gate area; an insulated area, adjacent to the gate area; a source region and a drain region made by silicon germanium, respectively, adjacent to the second side of the insulated area; a channel area, adjacent to the insulated area and formed between the source region and the drain region; a conductive layer, electrically connected to the source region and the drain region, respectively; and a plurality of capping layers, connected between the conductive layer and the source/drain regions, wherein the silicon layer(s) and the silicon germanium layer(s) are stacked alternately, and of which a silicon layer contacts the source/drain silicon germanium regions, while a silicon germanium layer contacts the conductive layer. The present invention also provides a complementary metal oxide semiconductor transistor including the P-type field effect transistor mentioned above.Type: ApplicationFiled: October 3, 2014Publication date: March 3, 2016Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: WEN-YIN WENG, CHENG-TUNG HUANG, WEI-HENG HSU, YI-TING WU, YU-MING LIN, JEN-YU WANG
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Publication number: 20160003888Abstract: A method of characterizing a device may be used to determine a metal work function of the device according to a threshold voltage, a body effect, and an oxide capacitance of the device. The threshold voltage may be determined according to a current to voltage curve. The oxide capacitance may be determined according to a capacitor to voltage curve.Type: ApplicationFiled: July 2, 2014Publication date: January 7, 2016Inventors: Wen-Yin Weng, Wei-Heng Hsu, Cheng-Tung Huang, Yi-Ting Wu, Yu-Ming Lin, Jen-Yu Wang