Abstract: A method of processing chips is disclosed. In one example, the method comprises encapsulating mutually spaced chips by an encapsulant comprising a locally curable material. The encapsulated chips with the encapsulant are separated into a plurality of encapsulated chip sections by locally curing selectively portions of the encapsulant covering at least a portion of the chips without curing other portions of the encapsulant apart from the encapsulated chip sections.

Abstract: Devices and methods are described for a contrast tray and framing devices for use with imagers. Some embodiments describe a contrast tray for use with an imager comprising one or more light diffusing layers configured to shift at least some of an imaging light and one or more light filtering layers configured to filter out at least some of the imaging light. Light diffusing and light filtering layers can be further configured to upconvert at least some of the diffused and/or non-filtered light. Contrast trays can be used to improve imaging of gels such as PAGE gels when using a green or blue-green light. Other embodiments of the disclosure describe a framing device that provides better illumination and lower background fluorescence for fluorescent gels, such as nucleic acid gels.

Abstract: A method for determining the performance of an implanting apparatus comprises the steps of forming a dopant barrier layer on a substrate, forming a target layer on the dopant barrier layer, performing an implanting process by using the implanting apparatus to implant dopants into the target layer such that the target layer becomes conductive, measuring at least one electrical property of the target layer, and determining the performance of the implanting apparatus by taking the electrical property into consideration. In one embodiment of the present invention, the dopant barrier layer is silicon nitride layer, the target layer is a polysilicon layer, and the electrical property is the sheet resistance of the conductive polysilicon layer.

Abstract: A method for preparing an integrated circuit structure performs a deposition process to form a precursor layer on a substrate, and the precursor layer has a phase transition property in a transition temperature region. Subsequently, a first thermal treating process is performed at a first temperature to transform the precursor layer into a polymorphous layer possessing a predetermined crystalline phase, and the first temperature is higher than an upper limit of the temperature of the transition temperature region.