Abstract: A modular headphone system includes a headband holding an earphone module at each end of two ends thereof, a circuit module formed of an active noise cancelling module, a Bluetooth module, high-frequency module and/or a multi-channel audio controller and detachably mounted in one earphone module, and a power module detachably mounted in the other earphone module. Each earphone module includes an earphone body pivotally connected to one end of the headband, a speaker holder mounted at the earphone body and electrically connected to the earphone body, a speaker mounted in the speaker holder and electrically connected to the speaker holder and an ear cushion covered on the speaker holder over the speaker.

Abstract: A modular headphone system includes a headband holding an earphone module at each end of two ends thereof, a circuit module formed of an active noise cancelling module, a Bluetooth module, high-frequency module and/or a multi-channel audio controller and detachably mounted in one earphone module, and a power module detachably mounted in the other earphone module. Each earphone module includes an earphone body pivotally connected to one end of the headband, a speaker holder mounted at the earphone body and electrically connected to the earphone body, a speaker mounted in the speaker holder and electrically connected to the speaker holder and an ear cushion covered on the speaker holder over the speaker.

Abstract: An architecture is described for performing memory management in a virtualization environment. Multiple levels of caches are provided to perform address translations, where at least one of the caches contains a mapping between a guest virtual address and a host physical address. This type of caching implementation serves to minimize the need to perform costly multi-stage translations in a virtualization environment.

Abstract: An extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses is described, which includes both a set associative memory structure (SAM) and a content addressable memory (CAM) structure. An improved approach for operating an eTLB is described in which the same instruction is issued to perform the same task regardless of the exact underlying memory structure within the eTLB being accessed. For flush operations, the same instruction to perform a TLB flush can be provided to the eTLB that operates upon both the CAM and the SAM, which is then handled differently by the underlying implementation system of the eTLB depending upon whether the CAM and/or SAM is being accessed.

Abstract: An architecture and method are described for performing memory management. A page walker cache is provided to cache data used during the page walk process. This cache structure speeds up the page walk process, which significantly reduces the expense of performing a page walk. The page walker cache also reduces the cost associated with usage of memory access bandwidths.

Abstract: A system, method, and computer program product are provided for performing a register renaming operation utilizing hardware which operates in at least two modes. In operation, hardware is operated in at least two modes including a first mode for operating the hardware using a logical register of a first bit width and a second mode for operating the hardware using a logical register of a second bit width. The first bit width is twice a width of the second bit width. Additionally, a register renaming operation is performed, including renaming at least one logical register to at least one physical register of the first bit width, utilizing the hardware.

Abstract: A system for speculative branch predictions. An embodiment of the system includes branch prediction logic, fetch logic, and branch identification logic. The branch prediction logic is configured to predict a branch path for a branch in an instruction stream. The fetch logic is coupled to the branch prediction logic. The fetch logic is configured to speculatively fetch an instruction corresponding to the predicted branch path. The branch identification logic is coupled to the branch prediction logic and the fetch logic. The branch identification logic is configured to mark the speculatively fetched instruction with a branch identifier using a universal branch identification format. The universal branch identification format includes a bit value at a bit position corresponding to the predicted branch path.

Abstract: A system for speculative branch predictions. An embodiment of the system includes branch prediction logic, fetch logic, and branch identification logic. The branch prediction logic is configured to predict a branch path for a branch in an instruction stream. The fetch logic is coupled to the branch prediction logic. The fetch logic is configured to speculatively fetch an instruction corresponding to the predicted branch path. The branch identification logic is coupled to the branch prediction logic and the fetch logic. The branch identification logic is configured to mark the speculatively fetched instruction with a branch identifier using a universal branch identification format. The universal branch identification format includes a bit value at a bit position corresponding to the predicted branch path.